{"id":"https://openalex.org/W2141835763","doi":"https://doi.org/10.1109/isqed.2008.4479806","title":"An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign","display_name":"An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2141835763","doi":"https://doi.org/10.1109/isqed.2008.4479806","mag":"2141835763"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479806","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479806","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080659816","display_name":"Ming-Fang Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I2803006356","display_name":"Winbond (Taiwan)","ror":"https://ror.org/045100v05","country_code":"TW","type":"company","lineage":["https://openalex.org/I2803006356"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Ming-Fang Lai","raw_affiliation_strings":["Winbond Incorporation, Hsinchu, Taiwan","Winbond Incorporation, Hsinchu"],"affiliations":[{"raw_affiliation_string":"Winbond Incorporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I2803006356"]},{"raw_affiliation_string":"Winbond Incorporation, Hsinchu","institution_ids":["https://openalex.org/I2803006356"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021615416","display_name":"Hung-Ming Chen","orcid":"https://orcid.org/0000-0001-8173-3131"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Ming Chen","raw_affiliation_strings":["Department of EE and SoC Research Center, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of EE and SoC Research Center, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5080659816"],"corresponding_institution_ids":["https://openalex.org/I2803006356"],"apc_list":null,"apc_paid":null,"fwci":1.3318,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.8246817,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"604","last_page":"607"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.7628402709960938},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7627530097961426},{"id":"https://openalex.org/keywords/ibm","display_name":"IBM","score":0.7079785466194153},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7006846070289612},{"id":"https://openalex.org/keywords/flip-chip","display_name":"Flip chip","score":0.6510286331176758},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6280149221420288},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6170045733451843},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.5415814518928528},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5319098830223083},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4792885184288025},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.46815064549446106},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.4664914608001709},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42716941237449646},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4191301167011261},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.4181568920612335},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1813850998878479},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10016095638275146},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.08020302653312683}],"concepts":[{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.7628402709960938},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7627530097961426},{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.7079785466194153},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7006846070289612},{"id":"https://openalex.org/C79072407","wikidata":"https://www.wikidata.org/wiki/Q432439","display_name":"Flip chip","level":4,"score":0.6510286331176758},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6280149221420288},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6170045733451843},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.5415814518928528},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5319098830223083},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4792885184288025},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.46815064549446106},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.4664914608001709},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42716941237449646},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4191301167011261},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.4181568920612335},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1813850998878479},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10016095638275146},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.08020302653312683},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C68928338","wikidata":"https://www.wikidata.org/wiki/Q131790","display_name":"Adhesive","level":3,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479806","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479806","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1572439820","https://openalex.org/W1680287565","https://openalex.org/W1841949876","https://openalex.org/W1862552898","https://openalex.org/W1889909361","https://openalex.org/W1969208860","https://openalex.org/W1996746141","https://openalex.org/W2075265327","https://openalex.org/W2090146793","https://openalex.org/W2098851424","https://openalex.org/W2098868123","https://openalex.org/W2102502584","https://openalex.org/W2117148144","https://openalex.org/W2135251648","https://openalex.org/W2161314156","https://openalex.org/W4237886783","https://openalex.org/W4248245364","https://openalex.org/W6637124764"],"related_works":["https://openalex.org/W2250058922","https://openalex.org/W2898647956","https://openalex.org/W2811251486","https://openalex.org/W4239401071","https://openalex.org/W2067224723","https://openalex.org/W2533759086","https://openalex.org/W2094215088","https://openalex.org/W2097451288","https://openalex.org/W4255973033","https://openalex.org/W2246813539"],"abstract_inverted_index":{"As":[0],"silicon":[1],"technology":[2,26],"scales,":[3],"we":[4,78],"can":[5],"integrate":[6],"more":[7,9,17],"and":[8,82,89,98,117],"circuits":[10],"on":[11],"a":[12,63,80],"single":[13],"chip,":[14,64],"which":[15,27],"means":[16],"I/Os":[18],"are":[19],"needed":[20],"in":[21,72,87,120],"modern":[22],"designs.":[23],"The":[24,105],"flip-chip":[25,51],"was":[28],"developed":[29],"by":[30,70],"IBM":[31],"is":[32,53],"better":[33],"suited":[34],"for":[35,94,102],"I/O":[36,56,75,83],"increase":[37],"than":[38],"the":[39,46,55],"typical":[40],"peripheral":[41],"wire-bond":[42],"design.":[43],"One":[44],"of":[45,50,114],"most":[47],"important":[48],"characteristics":[49],"designs":[52],"that":[54,109],"buffers":[57],"could":[58],"be":[59],"placed":[60],"anywhere":[61],"inside":[62],"just":[65],"like":[66],"core":[67],"cells.":[68],"Motivated":[69],"[14]":[71],"proposing":[73],"various":[74],"planning":[76],"constraints,":[77],"develop":[79],"block":[81],"buffer":[84],"placement":[85],"method":[86],"wirelength":[88],"signal":[90],"skew":[91],"optimization":[92],"(especially":[93],"differential":[95],"pair":[96],"signals),":[97],"power":[99,115],"integrity":[100,116],"awareness":[101],"chip-package":[103],"codesign.":[104],"results":[106],"have":[107],"shown":[108],"our":[110],"approach":[111],"takes":[112],"care":[113],"outperforms":[118],"[12]":[119],"weighted":[121],"performance":[122],"metrics":[123],"optimization.":[124]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
