{"id":"https://openalex.org/W2016434845","doi":"https://doi.org/10.1109/isqed.2008.4479800","title":"Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test","display_name":"Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2016434845","doi":"https://doi.org/10.1109/isqed.2008.4479800","mag":"2016434845"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088567598","display_name":"Sanjiv Taneja","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sanjiv Taneja","raw_affiliation_strings":["GM Encounter Test business unit Cadence Design Systems","Cadence Design Systems, San Jose"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"GM Encounter Test business unit Cadence Design Systems","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems, San Jose","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5088567598"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"585","last_page":"585"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronics","display_name":"Electronics","score":0.6174626350402832},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6100723743438721},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5691518783569336},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.46927180886268616},{"id":"https://openalex.org/keywords/pace","display_name":"Pace","score":0.42245739698410034},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4209812581539154},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4101998805999756},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.3897751569747925},{"id":"https://openalex.org/keywords/manufacturing-engineering","display_name":"Manufacturing engineering","score":0.37828683853149414},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3557836413383484},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3500036299228668},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3248720169067383},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2722170352935791},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.19343960285186768}],"concepts":[{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.6174626350402832},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6100723743438721},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5691518783569336},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46927180886268616},{"id":"https://openalex.org/C2777526511","wikidata":"https://www.wikidata.org/wiki/Q691543","display_name":"Pace","level":2,"score":0.42245739698410034},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4209812581539154},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4101998805999756},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3897751569747925},{"id":"https://openalex.org/C117671659","wikidata":"https://www.wikidata.org/wiki/Q11049265","display_name":"Manufacturing engineering","level":1,"score":0.37828683853149414},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3557836413383484},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3500036299228668},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3248720169067383},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2722170352935791},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.19343960285186768},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3011978806","https://openalex.org/W3204573923","https://openalex.org/W3207169898","https://openalex.org/W2743305891","https://openalex.org/W2019954703","https://openalex.org/W4385309418","https://openalex.org/W192757576","https://openalex.org/W2331259470","https://openalex.org/W3198354237","https://openalex.org/W2489638043"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2,154],"given.":[3],"Test":[4,51],"has":[5,26,52],"long":[6],"been":[7,54],"recognized":[8],"as":[9],"the":[10,31,36,47,57,87,115,134,137,158],"bridge":[11],"between":[12],"design":[13,22,41,116,128,159],"and":[14,18,23,35,42,72,91,106,129,166,175,178],"manufacturing.":[15,43],"However,":[16],"innovation":[17],"deep":[19],"integration":[20],"in":[21,77],"test":[24],"tools":[25],"not":[27,53,153],"kept":[28],"pace":[29],"with":[30,125],"consumerization":[32,61],"of":[33,50,62,83,94,139],"electronics":[34,63],"rapidly":[37],"evolving":[38],"nanometer":[39,78],"IC":[40],"As":[44],"a":[45,103,107,118],"result,":[46],"full":[48],"potential":[49],"harnessed":[55,144],"by":[56],"mainstream":[58],"semiconductor":[59],"community.The":[60],"places":[64],"significant":[65],"new":[66,104],"demands":[67],"on":[68],"low":[69,126],"power,":[70],"correctness":[71],"time-to-volume":[73],"production.The":[74],"rapid":[75,146],"advances":[76],"technologies":[79],"pose":[80],"additional":[81],"set":[82],"challenges":[84,174],"due":[85],"to":[86,101,110],"advanced":[88],"physics":[89],"effects":[90],"higher":[92],"scales":[93],"transistor":[95],"integration.":[96],"The":[97],"EDA":[98],"industry":[99],"needs":[100],"establish":[102],"paradigm":[105],"\"deep":[108],"integration\"":[109],"meet":[111],"these":[112,173],"challenges.":[113],"During":[114],"phase,":[117,136],"power-aware":[119],"DFT":[120,140],"architecture":[121],"must":[122,141],"integrate":[123],"tightly":[124],"power":[127,167],"implementation":[130],"flow.":[131],"Later,":[132],"during":[133],"manufacturing":[135],"benefits":[138],"be":[142],"seamlessly":[143],"for":[145],"scan":[147],"diagnostics":[148],"based":[149],"yield":[150],"learning":[151],"using":[152,163],"logic":[155],"information":[156],"from":[157],"database":[160],"but":[161],"also":[162],"layout":[164],"timing":[165],"information.":[168],"This":[169],"keynote":[170],"will":[171],"discuss":[172],"possible":[176],"solutions":[177],"scenarios.":[179]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
