{"id":"https://openalex.org/W2034281864","doi":"https://doi.org/10.1109/isqed.2008.4479777","title":"System Verilog for Quality of Results (QoR)","display_name":"System Verilog for Quality of Results (QoR)","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2034281864","doi":"https://doi.org/10.1109/isqed.2008.4479777","mag":"2034281864"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479777","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479777","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098090931","display_name":"Ravi Surepeddi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210101851","display_name":"Magma (Germany)","ror":"https://ror.org/016a8y628","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210101851"]},{"id":"https://openalex.org/I4210126997","display_name":"Software and Engineering Associates (United States)","ror":"https://ror.org/03qt0ma29","country_code":"US","type":"company","lineage":["https://openalex.org/I4210126997"]}],"countries":["DE","US"],"is_corresponding":true,"raw_author_name":"Ravi Surepeddi","raw_affiliation_strings":["Magma Design-Automation, Inc., USA","Magma Design Automation Inc., San Jose#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Magma Design-Automation, Inc., USA","institution_ids":[]},{"raw_affiliation_string":"Magma Design Automation Inc., San Jose#TAB#","institution_ids":["https://openalex.org/I4210101851","https://openalex.org/I4210126997"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5098090931"],"corresponding_institution_ids":["https://openalex.org/I4210101851","https://openalex.org/I4210126997"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.0568915,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"460","last_page":"464"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8140881657600403},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7580783367156982},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.5141775608062744},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5129010677337646},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.5015461444854736},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48011350631713867},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4703255891799927},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.43592286109924316},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.37338414788246155},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3195861577987671},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.21925553679466248},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19390007853507996}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8140881657600403},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7580783367156982},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.5141775608062744},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5129010677337646},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.5015461444854736},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48011350631713867},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4703255891799927},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.43592286109924316},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.37338414788246155},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3195861577987671},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.21925553679466248},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19390007853507996},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479777","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479777","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2070693700","https://openalex.org/W2119527718","https://openalex.org/W2105593427","https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W2106507440","https://openalex.org/W2108860137","https://openalex.org/W3209085687","https://openalex.org/W2078880479","https://openalex.org/W2153955347"],"abstract_inverted_index":{"Design":[0],"complexity":[1],"is":[2,27,75],"ever":[3],"increasing":[4],"with":[5],"multi-":[6],"mode,":[7],"statistical":[8],"timing":[9],"analysis,":[10],"multi-vt/VDD":[11],"low":[12,208],"power":[13,209],"and":[14,36,42,194,203],"multi-core":[15],"performance":[16],"based":[17,185],"type":[18],"of":[19,103,114,129,154],"designs.":[20],"IEEE":[21],"1800":[22],"system":[23,39,98],"verilog":[24,34,56],"(Ref":[25],"1)":[26,142],"a":[28,178,183],"natural":[29],"smooth":[30],"transition":[31],"language":[32],"to":[33,149,176,182],"(Refi":[35],"3)":[37,174],"for":[38,50,67,82,97,107,126,137,166],"level":[40,191],"design":[41,52,72,83,89,104,109,123,127,138,210],"verification.":[43],"Verilog":[44],"RTL":[45,95],"has":[46],"been":[47],"popularly":[48],"used":[49,81],"many":[51,88],"tape":[53,84],"outs.":[54],"System":[55,190],"(SV)":[57],"extensive":[58],"support":[59],"exists":[60],"in":[61,112,151],"verification":[62,115],"tools":[63],"viz.":[64],"simulators,":[65],"formal":[66],"various":[68,108,121],"powerful":[69],"SV":[70,78,93,122],"specific":[71,94,124,134],"constructs.":[73],"It":[74],"envisaged":[76],"that":[77],"will":[79],"be":[80],"outs":[85],"soon":[86],"as":[87],"houses":[90],"started":[91],"using":[92,145,196],"constructs":[96,125,135],"designs":[99],"involving":[100],"high":[101],"levels":[102],"data":[105,155],"abstractions":[106],"application":[110],"keeping":[111],"view":[113],"support.":[116],"This":[117],"paper":[118],"analyzes":[119],"on":[120,186],"quality":[128],"results":[130],"(QOR)":[131],"improvement.":[132],"The":[133],"discussed":[136],"QOR":[139,187],"improvements":[140],"are":[141],"operator":[143],"overloading":[144],"user":[146],"defined":[147],"types":[148],"bring":[150],"efficient":[152,180],"implementation":[153],"path":[156],"operators":[157],"like":[158],"multiplier,":[159],"adder,":[160],"shift,..":[161],"2)":[162],"Parameterized":[163],"module":[164,184],"interface":[165,193],"different":[167],"sized":[168],"datapath,":[169],"memory,":[170],"fifo,":[171],"register":[172],"files..":[173],"Configuration":[175],"bind":[177],"particular":[179],"architecture":[181],"requirement":[188],"4)":[189],"modules":[192],"arbitration":[195],"\"interface\"construct.":[197],"5)":[198],"Multiple":[199],"clock":[200],"domain":[201],"definition":[202],"interface.":[204],"6)":[205],"IEEE1801":[206],"UPF":[207],"intent":[211],"flow.":[212]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}