{"id":"https://openalex.org/W2031402563","doi":"https://doi.org/10.1109/isqed.2008.4479760","title":"Computation of Waveform Sensitivity Using Geometric Transforms for SSTA","display_name":"Computation of Waveform Sensitivity Using Geometric Transforms for SSTA","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2031402563","doi":"https://doi.org/10.1109/isqed.2008.4479760","mag":"2031402563"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479760","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479760","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100893618","display_name":"Ratnakar Goyal","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Ratnakar Goyal","raw_affiliation_strings":["Cadence Design Systems (India) Private Limited, India","Cadence Design Syst. (India) Pvt. Ltd., New Delhi"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems (India) Private Limited, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Syst. (India) Pvt. Ltd., New Delhi","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048990173","display_name":"Harindranath Parameswaran","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Harindranath Parameswaran","raw_affiliation_strings":["Cadence Design Systems (India) Private Limited, India","Cadence Design Syst. (India) Pvt. Ltd., New Delhi"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems (India) Private Limited, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Syst. (India) Pvt. Ltd., New Delhi","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108870800","display_name":"Sachin Shrivastava","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Sachin Shrivastava","raw_affiliation_strings":["Cadence Design Systems (India) Private Limited, India","Cadence Design Syst. (India) Pvt. Ltd., New Delhi"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems (India) Private Limited, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Cadence Design Syst. (India) Pvt. Ltd., New Delhi","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4744,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.53409894,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"373","last_page":"378"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.9493900537490845},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7061947584152222},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7012820839881897},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.6707605719566345},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5729386210441589},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5143724679946899},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.47719037532806396},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.45027250051498413},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.41167202591896057},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3805282711982727},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3244381248950958},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.27180254459381104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15306898951530457}],"concepts":[{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.9493900537490845},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7061947584152222},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7012820839881897},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.6707605719566345},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5729386210441589},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5143724679946899},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.47719037532806396},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.45027250051498413},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.41167202591896057},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3805282711982727},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3244381248950958},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.27180254459381104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15306898951530457},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479760","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479760","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1833135688","https://openalex.org/W2057369721","https://openalex.org/W2074952123","https://openalex.org/W2115047803","https://openalex.org/W2163262735","https://openalex.org/W4247494086","https://openalex.org/W4247815215","https://openalex.org/W4289256183","https://openalex.org/W6641884055"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W2031402563","https://openalex.org/W2101495896","https://openalex.org/W2751669468","https://openalex.org/W2132750868","https://openalex.org/W2145535176","https://openalex.org/W4246714407","https://openalex.org/W1947426333","https://openalex.org/W1804063983","https://openalex.org/W2134944363"],"abstract_inverted_index":{"With":[0],"shrinking":[1],"process":[2,9,106,127,176],"node":[3],"sizes,":[4],"the":[5,18,28,41,57,74,81,86,90,103,110,166,170,182,211,220,229,246,273,284],"inherent":[6],"effect":[7,104],"of":[8,20,30,43,48,53,59,73,85,145,159,184,210,228,248,281,286],"variations":[10,107],"is":[11,207,255],"playing":[12],"a":[13,21,37,44,65,156,196,249,262],"larger":[14],"factor":[15],"in":[16,27,46,77,89,121,132,165,179,232,283],"defining":[17],"behavior":[19],"circuit":[22,45],"and":[23,83,219],"this":[24,192],"has":[25],"resulted":[26],"promotion":[29],"statistical":[31,66,94,250,263],"static":[32],"timing":[33,49,60,91,112,133,167,230],"analysis":[34,203],"(SSTA)":[35],"as":[36,62,259],"method":[38],"for":[39,135,142,149,198],"estimating":[40],"yield":[42],"terms":[47],"activities.":[50],"The":[51,71],"accuracy":[52,58,72,82,279],"SSTA":[54],"depends":[55,79],"on":[56,80,102,109],"sensitivities":[61,139,148,164,186,201,227,276],"computed":[63,274],"using":[64,243],"delay":[67,116,147,234],"calculation":[68],"(S-DC)":[69],"engine.":[70],"S-DC":[75],"engine":[76],"turn":[78],"availability":[84],"required":[87,141],"information":[88,101,206],"library.":[92,214],"For":[93],"analysis,":[95],"these":[96],"libraries":[97],"need":[98],"to":[99,129,236,261],"contain":[100],"that":[105,242,272],"have":[108],"library":[111,134,168,171,251,264],"data.":[113],"New":[114],"generation":[115],"calculators":[117],"also":[118,270],"require":[119],"change":[120],"waveform":[122,163,185,200,222,238,267,275],"shape":[123],"(waveform":[124],"sensitivity)":[125],"with":[126,225,252,265],"variation":[128],"be":[130,189],"modeled":[131],"better":[136],"accuracy.":[137],"Waveform":[138],"are":[140],"accurate":[143],"computation":[144,285],"gate":[146],"gates":[150],"driving":[151],"large":[152,157],"interconnect":[153],"loads":[154],"or":[155],"number":[158],"fanouts.":[160],"However,":[161],"modeling":[162],"increases":[169],"size":[172,247],"significantly":[173],"(~40%":[174],"per":[175],"parameter).":[177],"Also":[178],"different":[180],"scenarios":[181],"characterization":[183],"may":[187],"not":[188,208],"possible.":[190],"In":[191],"paper,":[193],"we":[194],"propose":[195],"technique":[197],"computing":[199],"during":[202],"when":[204],"such":[205],"part":[209],"standard":[212,287],"cell":[213],"We":[215,240,269],"use":[216],"geometric":[217],"transforms":[218],"nominal":[221],"information,":[223],"along":[224],"available":[226],"activities":[231],"non-linear":[233],"models":[235],"derive":[237],"sensitivities.":[239,268],"show":[241,271],"our":[244],"approach":[245],"700":[253],"cells":[254],"reduced":[256],"by":[257],"~65%":[258],"compared":[260],"characterized":[266],"provide":[277],"an":[278],"improvement":[280],"15-20%":[282],"deviation.":[288]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}