{"id":"https://openalex.org/W2113508119","doi":"https://doi.org/10.1109/isqed.2008.4479749","title":"Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies","display_name":"Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2113508119","doi":"https://doi.org/10.1109/isqed.2008.4479749","mag":"2113508119"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479749","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028197292","display_name":"Srinivasa R STG","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Srinivasa R STG","raw_affiliation_strings":["MG-I, Intel Technology (I)(P) Ltd., Bangalore, India","Intel Technol. (I)(P) Ltd., Bangalore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MG-I, Intel Technology (I)(P) Ltd., Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Technol. (I)(P) Ltd., Bangalore","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074908240","display_name":"Srivatsava Jandhyala","orcid":"https://orcid.org/0000-0002-1497-7264"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Jandhyala Srivatsava","raw_affiliation_strings":["MG-I, Intel Technology (I)(P) Ltd., Bangalore, India","Intel Technol. (I)(P) Ltd., Bangalore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MG-I, Intel Technology (I)(P) Ltd., Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Technol. (I)(P) Ltd., Bangalore","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111904672","display_name":"Narahari Tondamuthuru R","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Narahari Tondamuthuru R","raw_affiliation_strings":["MG-I, Intel Technology (I)(P) Ltd., Bangalore, India","Intel Technol. (I)(P) Ltd., Bangalore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MG-I, Intel Technology (I)(P) Ltd., Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Intel Technol. (I)(P) Ltd., Bangalore","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4233,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.78600501,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"325","last_page":"329"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.927353024482727},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.7768334746360779},{"id":"https://openalex.org/keywords/derating","display_name":"Derating","score":0.7453283071517944},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6765117645263672},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.6567922234535217},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5706788301467896},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.5617111921310425},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5525255799293518},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5143488645553589},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4592433273792267},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4508379399776459},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33856281638145447},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25658124685287476},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16090187430381775},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10660290718078613}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.927353024482727},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.7768334746360779},{"id":"https://openalex.org/C70500001","wikidata":"https://www.wikidata.org/wiki/Q1199915","display_name":"Derating","level":3,"score":0.7453283071517944},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6765117645263672},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.6567922234535217},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5706788301467896},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.5617111921310425},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5525255799293518},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5143488645553589},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4592433273792267},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4508379399776459},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33856281638145447},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25658124685287476},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16090187430381775},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10660290718078613},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479749","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1846979026","https://openalex.org/W2117648153","https://openalex.org/W2123355738","https://openalex.org/W2125263803"],"related_works":["https://openalex.org/W4251264894","https://openalex.org/W3192656014","https://openalex.org/W2095646370","https://openalex.org/W2388589331","https://openalex.org/W2545489593","https://openalex.org/W4246351405","https://openalex.org/W1970762549","https://openalex.org/W2549099758","https://openalex.org/W2366713167","https://openalex.org/W1569991298"],"abstract_inverted_index":{"Integrated":[0],"circuit":[1],"manufacturability":[2],"in":[3,31,38],"DSM":[4,32],"is":[5],"directly":[6],"dependent":[7],"on":[8,62,84],"how":[9],"well":[10],"the":[11,18,25,58,63,80,95,106,118],"manufacturing":[12],"variations":[13,30,37,88,97],"are":[14,71,89],"accounted":[15],"for":[16,108,117],"during":[17],"design":[19],"of":[20,27,75,82,94],"circuits.":[21],"This":[22],"paper":[23],"reviews":[24],"effect":[26,81],"various":[28],"process":[29,40],"especially":[33],"systematic":[34],"and":[35,53,101,112],"random":[36],"three":[39],"generations":[41],"90":[42],"nm,":[43],"65":[44],"nm":[45,48,100],"&":[46],"45":[47,99],"by":[49],"doing":[50],"SPICE":[51],"simulation":[52],"analysis":[54,115],"to":[55,65,78],"look":[56],"at":[57,98],"derating":[59],"factors":[60],"depending":[61],"sensitivity":[64],"variations.":[66],"Few":[67],"individual":[68],"standard":[69],"cells":[70],"studied":[72],"as":[73],"apart":[74],"this":[76],"exercise":[77],"see":[79],"variation":[83,113],"their":[85],"delays.":[86],"Random":[87],"becoming":[90],"a":[91],"significant":[92],"portion":[93],"overall":[96],"below.":[102],"The":[103],"results":[104],"suggests":[105],"need":[107],"selective,":[109],"location":[110],"based":[111],"aware":[114],"(SLVA)":[116],"designs":[119],"going":[120],"forward.":[121]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
