{"id":"https://openalex.org/W2103749050","doi":"https://doi.org/10.1109/isqed.2008.4479726","title":"A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations","display_name":"A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2103749050","doi":"https://doi.org/10.1109/isqed.2008.4479726","mag":"2103749050"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479726","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479726","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113692137","display_name":"Amit Goel","orcid":"https://orcid.org/0009-0003-2338-3083"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Goel","raw_affiliation_strings":["Department of Computer Science and Engineering, Arizona State university, Tempe, AZ, USA","Arizona State University, Tempe,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Arizona State university, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]},{"raw_affiliation_string":"Arizona State University, Tempe,#TAB#","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030130819","display_name":"Sarma Vrudhula","orcid":"https://orcid.org/0000-0001-9278-2959"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarma Vrudhula","raw_affiliation_strings":["Department of Computer Science and Engineering, Arizona State university, Tempe, AZ, USA","Arizona State University, Tempe,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Arizona State university, Tempe, AZ, USA","institution_ids":["https://openalex.org/I55732556"]},{"raw_affiliation_string":"Arizona State University, Tempe,#TAB#","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029114289","display_name":"Feroze Taraporevala","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Feroze Taraporevala","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA","Synopsys, Inc. Mountain View, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys, Inc. Mountain View, CA#TAB#","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016520937","display_name":"Praveen Ghanta","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Praveen Ghanta","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA","Synopsys, Inc. Mountain View, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys, Inc. Mountain View, CA#TAB#","institution_ids":["https://openalex.org/I1335490905"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4233,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.78124701,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"200","last_page":"206"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.809005856513977},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6942581534385681},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.5983896851539612},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.596289873123169},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.595722496509552},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5720453858375549},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.48814496397972107},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4644935429096222},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4172241687774658},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4117983877658844},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3692377805709839},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2600034177303314},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16351613402366638},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08976781368255615}],"concepts":[{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.809005856513977},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6942581534385681},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.5983896851539612},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.596289873123169},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.595722496509552},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5720453858375549},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.48814496397972107},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4644935429096222},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4172241687774658},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4117983877658844},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3692377805709839},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2600034177303314},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16351613402366638},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08976781368255615},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479726","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479726","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1667165204","https://openalex.org/W1979020681","https://openalex.org/W2061048205","https://openalex.org/W2065183790","https://openalex.org/W2087773252","https://openalex.org/W2117829742","https://openalex.org/W2126564504","https://openalex.org/W2137692539","https://openalex.org/W2146731180","https://openalex.org/W2147120839","https://openalex.org/W2171353459","https://openalex.org/W2752128027","https://openalex.org/W2752719613","https://openalex.org/W3149376625","https://openalex.org/W4237084751","https://openalex.org/W4237955880","https://openalex.org/W4240732800","https://openalex.org/W4251935962","https://openalex.org/W6644777513","https://openalex.org/W6672556086","https://openalex.org/W6678664461"],"related_works":["https://openalex.org/W2146978563","https://openalex.org/W2101197344","https://openalex.org/W2033560541","https://openalex.org/W2160885012","https://openalex.org/W2126607849","https://openalex.org/W1569991298","https://openalex.org/W2161199482","https://openalex.org/W2002611358","https://openalex.org/W2315780722","https://openalex.org/W2039420321"],"abstract_inverted_index":{"Integrated":[0],"circuits":[1],"today":[2],"rely":[3],"on":[4,22,98],"extensive":[5],"re-use":[6],"of":[7,34,67,77,89,102],"pre-characterized":[8,90],"IP":[9,35],"bocks":[10],"and":[11,37,47,58,63,105,113],"macro":[12,38],"cells":[13,39],"to":[14],"meet":[15],"the":[16,68],"demand":[17],"for":[18,32,40,54,85,117],"high":[19],"performance":[20],"system":[21],"chip":[23],"(SoC).":[24],"In":[25],"this":[26],"paper":[27],"we":[28],"propose":[29,82],"a":[30,83],"methodology":[31],"characterization":[33,76],"blocks":[36],"statistical":[41],"timing":[42,91],"analysis":[43],"considering":[44],"process":[45,69],"variations":[46,60],"spatial":[48],"correlations.":[49],"We":[50,81],"develop":[51],"efficient":[52],"models":[53],"capturing":[55],"both":[56],"inter-die":[57],"intra-die":[59],"in":[61,71,109],"devices":[62],"interconnects.":[64],"Increasing":[65],"variability":[66],"parameters":[70],"sub-nanometer":[72],"designs":[73,101],"requires":[74],"instance-specific":[75],"these":[78],"design":[79],"blocks.":[80],"technique":[84],"instance-":[86],"specific":[87],"calibration":[88],"model.":[92],"The":[93],"proposed":[94],"approach":[95],"was":[96],"evaluated":[97],"large":[99],"industrial":[100],"1.2":[103],"M":[104,107],"3.5":[106],"gates":[108],"65":[110],"nm":[111],"technology":[112],"validated":[114],"against":[115],"SPICE":[116],"accuracy.":[118]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
