{"id":"https://openalex.org/W2129523677","doi":"https://doi.org/10.1109/isqed.2008.4479715","title":"Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic","display_name":"Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2129523677","doi":"https://doi.org/10.1109/isqed.2008.4479715","mag":"2129523677"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479715","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074738133","display_name":"Kumar Yelamarthi","orcid":"https://orcid.org/0000-0002-0072-3909"},"institutions":[{"id":"https://openalex.org/I19648265","display_name":"Wright State University","ror":"https://ror.org/04qk6pt94","country_code":"US","type":"education","lineage":["https://openalex.org/I19648265"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kumar Yelamarthi","raw_affiliation_strings":["Department of Electrical Engineering, Wright State University, Dayton, OH, USA","Wright State, University Dayton,"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Wright State University, Dayton, OH, USA","institution_ids":["https://openalex.org/I19648265"]},{"raw_affiliation_string":"Wright State, University Dayton,","institution_ids":["https://openalex.org/I19648265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064237316","display_name":"Chien\u2010In Henry Chen","orcid":"https://orcid.org/0000-0002-2304-7237"},"institutions":[{"id":"https://openalex.org/I19648265","display_name":"Wright State University","ror":"https://ror.org/04qk6pt94","country_code":"US","type":"education","lineage":["https://openalex.org/I19648265"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chien-In Henry Chen","raw_affiliation_strings":["Department of Electrical Engineering, Wright State University, Dayton, OH, USA","Wright State, University Dayton,"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Wright State University, Dayton, OH, USA","institution_ids":["https://openalex.org/I19648265"]},{"raw_affiliation_string":"Wright State, University Dayton,","institution_ids":["https://openalex.org/I19648265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074738133"],"corresponding_institution_ids":["https://openalex.org/I19648265"],"apc_list":null,"apc_paid":null,"fwci":1.6647,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.84960662,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"143","last_page":"147"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6983332633972168},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6854214072227478},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6808093786239624},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6198219060897827},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.6013652086257935},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5986025333404541},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5586107969284058},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5491703152656555},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5478640198707581},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.5438221096992493},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.522556483745575},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5027220249176025},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4459953308105469},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4315783381462097},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4196990728378296},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4139305353164673},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.39199358224868774},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.38156408071517944},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3689945936203003},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.31604886054992676},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29325681924819946},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25646042823791504},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22795000672340393},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16954398155212402},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11283096671104431}],"concepts":[{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6983332633972168},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6854214072227478},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6808093786239624},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6198219060897827},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.6013652086257935},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5986025333404541},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5586107969284058},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5491703152656555},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5478640198707581},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.5438221096992493},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.522556483745575},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5027220249176025},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4459953308105469},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4315783381462097},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4196990728378296},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4139305353164673},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.39199358224868774},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.38156408071517944},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3689945936203003},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.31604886054992676},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29325681924819946},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25646042823791504},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22795000672340393},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16954398155212402},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11283096671104431},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479715","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W275470402","https://openalex.org/W1508076293","https://openalex.org/W1569550779","https://openalex.org/W1989859908","https://openalex.org/W2033443176","https://openalex.org/W2092693137","https://openalex.org/W2105755487","https://openalex.org/W2108790707","https://openalex.org/W2117648153","https://openalex.org/W2129230692","https://openalex.org/W2133877139","https://openalex.org/W2149661268","https://openalex.org/W2150547314","https://openalex.org/W2171839588","https://openalex.org/W4241858902","https://openalex.org/W6634336121"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W1927636319","https://openalex.org/W3015599398","https://openalex.org/W2792778858","https://openalex.org/W2188730438","https://openalex.org/W2367816239","https://openalex.org/W2134944363","https://openalex.org/W1804063983","https://openalex.org/W2034656493","https://openalex.org/W1875529755"],"abstract_inverted_index":{"A":[0,99],"major":[1],"challenge":[2],"in":[3,12,35],"the":[4,27,36,69,88,110,136,147,152],"design":[5],"of":[6,20,26,32,55,67,108],"microprocessor":[7],"circuits":[8],"is":[9,58],"transistor":[10,46],"sizing":[11,47],"dynamic":[13,50],"CMOS":[14,51,144],"logic":[15],"due":[16,91],"to":[17,77,92,118,141,156],"increased":[18,30],"number":[19],"channel-connected":[21],"transistors":[22],"on":[23],"various":[24],"paths":[25],"design,":[28],"and":[29,87,128,151,159],"magnitude":[31],"process":[33,43,93],"variations":[34],"nanometer":[37],"process.":[38],"This":[39],"paper":[40],"proposes":[41],"a":[42,62,83,124,142],"variation":[44,94],"aware":[45],"algorithm":[48,57,140],"for":[49,82,123],"logic.":[52],"The":[53],"efficiency":[54],"this":[56],"illustrated":[59],"first":[60],"by":[61,97,133],"2-b":[63],"weighted":[64],"binary-to-thermometric":[65,103],"converter,":[66],"which":[68,80,109,121],"critical":[70,111,148],"path":[71,112,149],"delay":[72,85,89,113,126,129,150],"was":[73,95,105,114,131],"optimized":[74,96,132,155],"from":[75,116],"355":[76],"157":[78],"ps":[79,120,158],"accounts":[81,122],"55.77%":[84],"improvement,":[86,127],"uncertainty":[90,130],"60.75%.":[98],"4-b":[100],"unity":[101],"weight":[102],"converter":[104],"also":[106],"optimized,":[107],"reduced":[115],"152":[117],"103":[119],"32.23%":[125],"63.6%.":[134],"Applying":[135],"proposed":[137],"timing":[138],"optimization":[139],"mixed-dynamic-static":[143],"64-bit":[145],"adder,":[146],"power-delay-product":[153],"were":[154],"632":[157],"84.17":[160],"pJ,":[161],"respectively.":[162]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}