{"id":"https://openalex.org/W2123421630","doi":"https://doi.org/10.1109/isqed.2008.4479700","title":"Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes","display_name":"Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2123421630","doi":"https://doi.org/10.1109/isqed.2008.4479700","mag":"2123421630"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479700","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101923819","display_name":"Avijit Dutta","orcid":"https://orcid.org/0000-0003-2672-7331"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Avijit Dutta","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036507220","display_name":"Abhijit Jas","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abhijit Jas","raw_affiliation_strings":["Intel Corporation, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.20312231,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"35","issue":null,"first_page":"68","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7470647096633911},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6752689480781555},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.6627384424209595},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5546786785125732},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.5529289245605469},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.49991321563720703},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45956000685691833},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4536168575286865},{"id":"https://openalex.org/keywords/parity-bit","display_name":"Parity bit","score":0.4242319166660309},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3423093557357788},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2543186545372009},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10456573963165283}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7470647096633911},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6752689480781555},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.6627384424209595},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5546786785125732},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.5529289245605469},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.49991321563720703},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45956000685691833},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4536168575286865},{"id":"https://openalex.org/C131521367","wikidata":"https://www.wikidata.org/wiki/Q625502","display_name":"Parity bit","level":2,"score":0.4242319166660309},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3423093557357788},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2543186545372009},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10456573963165283},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479700","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479700","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1541483005","https://openalex.org/W1876153050","https://openalex.org/W1906369229","https://openalex.org/W1967835393","https://openalex.org/W1976549722","https://openalex.org/W2004813763","https://openalex.org/W2047207707","https://openalex.org/W2097596884","https://openalex.org/W2098784703","https://openalex.org/W2106454585","https://openalex.org/W2116587035","https://openalex.org/W2121618685","https://openalex.org/W2123949947","https://openalex.org/W2130919049","https://openalex.org/W2133687702","https://openalex.org/W2137211463","https://openalex.org/W2140430634","https://openalex.org/W2147942902","https://openalex.org/W2156689805","https://openalex.org/W2166267546","https://openalex.org/W2532367691","https://openalex.org/W2971174528","https://openalex.org/W2979917050","https://openalex.org/W4252162212","https://openalex.org/W6639535931","https://openalex.org/W6674877179"],"related_works":["https://openalex.org/W2995137536","https://openalex.org/W1749592617","https://openalex.org/W2537369590","https://openalex.org/W2116473596","https://openalex.org/W2007710086","https://openalex.org/W2110991008","https://openalex.org/W2126481660","https://openalex.org/W2068711101","https://openalex.org/W3182233882","https://openalex.org/W2358210862"],"abstract_inverted_index":{"Detecting":[0],"and":[1,18,87,102,109,148,160,177,205],"correcting":[2,161],"errors":[3,54,59,154],"in":[4,12,25,94],"logic":[5,32,186],"circuits":[6,33,187],"is":[7,55,81],"much":[8,36],"more":[9],"difficult":[10],"than":[11],"memories.":[13],"While":[14,92,119],"concurrent":[15,62],"error":[16,63,80,100,112,158],"detection":[17,64,113],"correction":[19],"mechanisms":[20],"can":[21,85,124,131,171],"be":[22,117,132,213],"efficiently":[23],"incorporated":[24],"memories":[26],"due":[27,51],"to":[28,46,52,56,146,182],"their":[29,41],"regular":[30],"structure,":[31],"present":[34],"a":[35,61,90,106,142],"greater":[37],"challenge":[38],"because":[39],"of":[40,75,194,219,226,237],"irregular":[42],"structure.":[43],"One":[44],"approach":[45,211],"handle":[47],"the":[48,58,69,73,79,83,129,136,150,167,174,179,209,220,227,235,238],"problems":[49],"arising":[50],"soft":[53,99,153],"detect":[57,147],"using":[60,155],"(CED)":[65],"circuitry":[66],"that":[67],"monitors":[68],"circuit":[70],"output":[71],"for":[72,103,135,185,223],"occurrence":[74],"an":[76,95],"error.":[77],"Once":[78],"detected":[82],"system":[84],"recover":[86],"hence":[88],"prevent":[89],"failure.":[91],"operating":[93],"environment":[96],"with":[97,105,188,202],"high":[98,134,203],"rate":[101,176],"systems":[104],"stringent":[107],"reliability":[108],"availability":[110,204],"requirement,":[111],"alone":[114],"may":[115],"not":[116],"sufficient.":[118],"triple":[120],"modular":[121],"redundancy":[122],"(TMR)":[123],"mask":[125],"all":[126],"single":[127],"faults,":[128],"overhead":[130],"unacceptably":[133],"targeted":[137],"applications.":[138],"This":[139],"paper":[140],"presents":[141],"low-overhead":[143],"non-intrusive":[144],"technique":[145],"correct":[149],"most":[151],"likely":[152],"customized":[156],"ad-hoc":[157],"detecting":[159],"(EDAC)":[162],"linear":[163],"block":[164],"codes.":[165],"Employing":[166],"proposed":[168,210,239],"EDAC":[169],"scheme":[170],"dramatically":[172],"reduce":[173],"failure":[175,183],"increase":[178],"mean":[180],"time":[181],"(MTTF)":[184],"limited":[189],"overhead.":[190],"For":[191],"certain":[192],"types":[193],"applications":[195],"e.g.,":[196],"network":[197],"servers,":[198,200],"query":[199],"etc.,":[201],"low":[206],"cost":[207],"requirements,":[208],"could":[212],"very":[214],"useful.":[215],"The":[216,231],"linearity":[217],"property":[218],"codes":[221],"allows":[222],"efficient":[224],"synthesis":[225],"parity":[228],"prediction":[229],"logic.":[230],"experimental":[232],"results":[233],"demonstrate":[234],"effectiveness":[236],"scheme.":[240]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}