{"id":"https://openalex.org/W2108172294","doi":"https://doi.org/10.1109/isqed.2008.4479696","title":"Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering","display_name":"Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2108172294","doi":"https://doi.org/10.1109/isqed.2008.4479696","mag":"2108172294"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054355893","display_name":"Tiago Muller Gil Cardoso","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Tiago Muller Gil Cardoso","raw_affiliation_strings":["Instituto de Inform\u00e1tica, UFRGS, Brazil"],"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, UFRGS, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103619904","display_name":"Felipe de Souza Marques","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Felipe de Souza Marques","raw_affiliation_strings":["Nangate Inc"],"affiliations":[{"raw_affiliation_string":"Nangate Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato Perez Ribas","raw_affiliation_strings":["UFRGS Instituto de Inform\u00e1tica"],"affiliations":[{"raw_affiliation_string":"UFRGS Instituto de Inform\u00e1tica","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andre Inacio Reis","raw_affiliation_strings":["Nangate Inc"],"affiliations":[{"raw_affiliation_string":"Nangate Inc","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leomar Soares da Rosa","raw_affiliation_strings":["Inst. de Inf. - UFRGS, Porto Alegre"],"affiliations":[{"raw_affiliation_string":"Inst. de Inf. - UFRGS, Porto Alegre","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5054355893"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":0.3329,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.64762692,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"47","last_page":"52"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8133242726325989},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7771725654602051},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6800549626350403},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5890419483184814},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5023279190063477},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46711429953575134},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4454779624938965},{"id":"https://openalex.org/keywords/logical-conjunction","display_name":"Logical conjunction","score":0.422904908657074},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.416364848613739},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4073820114135742},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36443889141082764},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.190434068441391},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17106324434280396},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1525343954563141},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07418438792228699}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8133242726325989},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7771725654602051},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6800549626350403},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5890419483184814},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5023279190063477},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46711429953575134},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4454779624938965},{"id":"https://openalex.org/C21847791","wikidata":"https://www.wikidata.org/wiki/Q191081","display_name":"Logical conjunction","level":2,"score":0.422904908657074},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.416364848613739},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4073820114135742},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36443889141082764},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.190434068441391},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17106324434280396},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1525343954563141},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07418438792228699},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479696","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479696","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1479741658","https://openalex.org/W1580033321","https://openalex.org/W1588576338","https://openalex.org/W1861481397","https://openalex.org/W1968414338","https://openalex.org/W1977850862","https://openalex.org/W2040537281","https://openalex.org/W2078179095","https://openalex.org/W2087907893","https://openalex.org/W2088115909","https://openalex.org/W2117686452","https://openalex.org/W2129042422","https://openalex.org/W2129501340","https://openalex.org/W2134849712","https://openalex.org/W2137321408","https://openalex.org/W2139352487","https://openalex.org/W2139358663","https://openalex.org/W2149214288","https://openalex.org/W2152063138","https://openalex.org/W2155214620","https://openalex.org/W2158020817","https://openalex.org/W2158491439","https://openalex.org/W2163156820","https://openalex.org/W2164012847"],"related_works":["https://openalex.org/W2134697552","https://openalex.org/W301738039","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871"],"abstract_inverted_index":{"This":[0,66],"paper":[1,95],"presents":[2],"a":[3,18,62,100],"method":[4,13,72],"for":[5],"speeding-up":[6],"ASICs":[7],"by":[8],"transistor":[9,24],"reordering.":[10],"The":[11,26,83],"proposed":[12],"can":[14,73,96],"be":[15,74,97],"applied":[16,39],"to":[17,40,81],"variety":[19],"of":[20,28,50,75,104],"logic":[21],"styles":[22],"and":[23],"topologies.":[25],"rationale":[27],"the":[29,48],"obtained":[30,60],"gains":[31,58],"is":[32,47],"explained":[33],"through":[34],"logical":[35,84],"effort":[36,85],"concepts.":[37],"When":[38],"circuits":[41],"based":[42],"on":[43,87],"4-input":[44],"networks,":[45],"which":[46],"case":[49],"many":[51],"structured-ASIC":[52],"or":[53],"FPGA":[54],"technologies,":[55],"significant":[56],"performance":[57],"are":[59],"at":[61],"small":[63],"area":[64],"expense.":[65],"observation":[67],"points":[68],"out":[69],"that":[70],"our":[71],"special":[76],"interest":[77],"when":[78],"migrating":[79],"FPGAs":[80],"ASICs.":[82],"effects":[86],"networks":[88],"derived":[89],"from":[90],"BDDs":[91],"illustrated":[92],"in":[93,99],"this":[94],"exploited":[98],"much":[101],"broader":[102],"range":[103],"designs.":[105]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
