{"id":"https://openalex.org/W2041907434","doi":"https://doi.org/10.1109/isqed.2008.4479688","title":"Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?","display_name":"Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2041907434","doi":"https://doi.org/10.1109/isqed.2008.4479688","mag":"2041907434"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109993342","display_name":"Hillary Hunter","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hillary Hunter","raw_affiliation_strings":["IBM, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5109993342"],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"7","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7702206373214722},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7625929713249207},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7207763195037842},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7135602831840515},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7008004188537598},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6344221234321594},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5682078003883362},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5244596004486084},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.48972800374031067},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4554663300514221},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.45021185278892517},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.43448519706726074},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4306790232658386},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.430219829082489},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3738570809364319},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.37352609634399414},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3045054078102112},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.23768013715744019},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.2149464190006256},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17272084951400757},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15029069781303406},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13537386059761047},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.13342303037643433}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7702206373214722},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7625929713249207},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7207763195037842},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7135602831840515},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7008004188537598},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6344221234321594},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5682078003883362},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5244596004486084},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.48972800374031067},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4554663300514221},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.45021185278892517},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.43448519706726074},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4306790232658386},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.430219829082489},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3738570809364319},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.37352609634399414},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3045054078102112},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.23768013715744019},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.2149464190006256},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17272084951400757},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15029069781303406},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13537386059761047},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.13342303037643433},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2516517078","https://openalex.org/W2150909864","https://openalex.org/W4382618825","https://openalex.org/W2161286015","https://openalex.org/W4386903460","https://openalex.org/W2900372418","https://openalex.org/W2924367614","https://openalex.org/W4211178602","https://openalex.org/W2127643145","https://openalex.org/W2149765501"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"Choosing":[4],"data":[5],"storage":[6,76],"arrays":[7],"for":[8,45],"a":[9,15,50],"microprocessor":[10,57],"design":[11,22],"is":[12,49,60],"driven":[13],"by":[14,63],"delicate":[16],"balance":[17],"of":[18,36,39,56],"technology":[19,93],"readiness,":[20],"circuit-level":[21],"factors,":[23],"and":[24,28,41,87,92,105,113],"system-level":[25],"performance,":[26],"power,":[27],"scaling":[29],"implications.":[30],"Recently,":[31],"CMOS":[32],"technologists":[33],"have":[34],"warned":[35],"the":[37,103,117],"\"end":[38],"scaling,\"":[40],"cite":[42],"particular":[43],"concern":[44],"six-transistor":[46],"SRAM.":[47],"This":[48,80],"startling":[51],"forecast,":[52],"since":[53],"easily":[54],"50%":[55],"silicon":[58],"area":[59],"commonly":[61],"occupied":[62],"SRAM":[64],"caches.":[65],"A":[66],"particularly":[67],"long-standing":[68],"debate":[69],"has":[70],"surrounded":[71],"one":[72],"dense,":[73],"resilient,":[74],"on-chip":[75],"alternative:":[77],"embedded":[78],"DRAM.":[79],"tutorial":[81],"will":[82],"provide":[83],"background":[84],"on":[85],"eDRAM,":[86],"show":[88],"how":[89],"its":[90],"circuit":[91],"properties":[94],"translate":[95],"to":[96,99],"metrics":[97],"used":[98],"make":[100],"decisions":[101],"at":[102],"chip":[104],"architecture":[106],"levels:":[107],"cache":[108,110,114],"capacity,":[109],"access":[111],"latency,":[112],"distance":[115],"from":[116],"CPU.":[118]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
