{"id":"https://openalex.org/W2163327726","doi":"https://doi.org/10.1109/isqed.2005.95","title":"Power Grid Planning for Microprocessors and SOCS","display_name":"Power Grid Planning for Microprocessors and SOCS","publication_year":2005,"publication_date":"2005-03-31","ids":{"openalex":"https://openalex.org/W2163327726","doi":"https://doi.org/10.1109/isqed.2005.95","mag":"2163327726"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2005.95","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2005.95","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixth International Symposium on Quality of Electronic Design (ISQED'05)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111649978","display_name":"Qing Zhu","orcid":"https://orcid.org/0009-0001-5322-1873"},"institutions":[{"id":"https://openalex.org/I4210158408","display_name":"Matrix Research (United States)","ror":"https://ror.org/04mw0p229","country_code":"US","type":"company","lineage":["https://openalex.org/I4210158408"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Qing K. Zhu","raw_affiliation_strings":["Matrix Semiconductor, Inc., Santa Clara, CA, USA","Matrix Semicond. Inc, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Matrix Semiconductor, Inc., Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210158408"]},{"raw_affiliation_string":"Matrix Semicond. Inc, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210158408"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066738995","display_name":"D. Ayers","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Ayers","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5111649978"],"corresponding_institution_ids":["https://openalex.org/I4210158408"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.2165824,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"352","last_page":"356"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.666944146156311},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.659061074256897},{"id":"https://openalex.org/keywords/power-grid","display_name":"Power grid","score":0.6585961580276489},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.643024206161499},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.6223138570785522},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5617302060127258},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4585016667842865},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.45548880100250244},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.43063294887542725},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3436623811721802},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32757946848869324},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23190441727638245},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09789326786994934}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.666944146156311},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.659061074256897},{"id":"https://openalex.org/C2983254600","wikidata":"https://www.wikidata.org/wiki/Q1096907","display_name":"Power grid","level":3,"score":0.6585961580276489},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.643024206161499},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.6223138570785522},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5617302060127258},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4585016667842865},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.45548880100250244},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.43063294887542725},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3436623811721802},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32757946848869324},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23190441727638245},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09789326786994934},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2005.95","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2005.95","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixth International Symposium on Quality of Electronic Design (ISQED'05)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.41999998688697815,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1602888171","https://openalex.org/W2018386086","https://openalex.org/W2065120607","https://openalex.org/W2090796734","https://openalex.org/W2111639188","https://openalex.org/W2124089733","https://openalex.org/W2150547314","https://openalex.org/W2163827229","https://openalex.org/W2476075474","https://openalex.org/W3150625878","https://openalex.org/W4242987207","https://openalex.org/W4245224483","https://openalex.org/W4245367739","https://openalex.org/W6826483172"],"related_works":["https://openalex.org/W2502691491","https://openalex.org/W2017236304","https://openalex.org/W2136854845","https://openalex.org/W2119122672","https://openalex.org/W4246278333","https://openalex.org/W4292904049","https://openalex.org/W4213404769","https://openalex.org/W4230312832","https://openalex.org/W2104315811","https://openalex.org/W2115579119"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"power":[3,28],"grid":[4,29],"planning":[5,30],"methodology":[6,58],"for":[7,36],"high-performance":[8],"microprocessors":[9],"and":[10,31,49],"SoC":[11,51],"chips.":[12],"It":[13],"shows":[14],"how":[15],"to":[16,23,38],"estimate":[17],"currents":[18],"from":[19],"an":[20],"existing":[21],"chip":[22,41],"a":[24],"new":[25],"chip.":[26],"The":[27],"pre-layout":[32],"simulation":[33],"becomes":[34],"important":[35],"time":[37],"market":[39],"of":[40],"design.":[42],"We":[43],"discuss":[44],"the":[45,57],"current":[46],"scaling":[47],"technique":[48],"one":[50],"design":[52],"example.":[53],"More":[54],"details":[55],"on":[56],"can":[59],"be":[60],"found":[61],"in":[62],"Zhu":[63],"(2004).":[64]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
