{"id":"https://openalex.org/W2107973438","doi":"https://doi.org/10.1109/isqed.2004.1283703","title":"Exact wiring fault minimization via comprehensive layout synthesis for CMOS logic cells","display_name":"Exact wiring fault minimization via comprehensive layout synthesis for CMOS logic cells","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W2107973438","doi":"https://doi.org/10.1109/isqed.2004.1283703","mag":"2107973438"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2004.1283703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2004.1283703","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007028121","display_name":"Tetsuya Iizuka","orcid":"https://orcid.org/0000-0002-1512-4714"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Iizuka","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Ikeda","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Asada","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"377","last_page":"380"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7359203100204468},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6514668464660645},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.6176380515098572},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5789429545402527},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5335496068000793},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4803815484046936},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4639202356338501},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4621674716472626},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4441477656364441},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4336867928504944},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4276009500026703},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42166370153427124},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3903079032897949},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38633447885513306},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27773481607437134},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18154260516166687},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.14831873774528503}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7359203100204468},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6514668464660645},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.6176380515098572},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5789429545402527},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5335496068000793},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4803815484046936},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4639202356338501},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4621674716472626},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4441477656364441},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4336867928504944},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4276009500026703},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42166370153427124},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3903079032897949},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38633447885513306},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27773481607437134},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18154260516166687},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.14831873774528503},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2004.1283703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2004.1283703","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1963294547","https://openalex.org/W1987067207","https://openalex.org/W2046812935","https://openalex.org/W2063553865","https://openalex.org/W2126428006","https://openalex.org/W2129555080","https://openalex.org/W4241865974"],"related_works":["https://openalex.org/W1553855433","https://openalex.org/W2098419840","https://openalex.org/W1852211506","https://openalex.org/W2121963733","https://openalex.org/W2356714888","https://openalex.org/W2136656113","https://openalex.org/W2160684472","https://openalex.org/W2170504327","https://openalex.org/W2127151832","https://openalex.org/W2066280488"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"an":[3],"exact":[4],"cell":[5],"layout":[6,57],"synthesis":[7],"technique":[8,72],"to":[9,17,92],"minimize":[10],"the":[11,22,31,37,45,54,64,77,82],"probability":[12,23],"of":[13,24,40,58,76],"wiring":[14],"faults":[15,25],"due":[16],"spot":[18,32],"defects.":[19],"We":[20],"modeled":[21],"on":[26],"intra-cell":[27],"routings":[28],"with":[29,81],"considering":[30],"defects":[33],"size":[34],"distribution":[35],"and":[36,62],"end":[38],"effect":[39],"critical":[41],"areas.":[42],"By":[43],"using":[44],"model":[46],"as":[47],"a":[48],"cost":[49],"function,":[50],"we":[51],"comprehensively":[52],"generate":[53],"minimum":[55],"width":[56],"CMOS":[59,86],"logic":[60,87],"cells":[61],"select":[63],"optimum":[65],"layouts.":[66],"Experimental":[67],"results":[68],"show":[69],"that":[70],"our":[71],"reduces":[73],"about":[74],"15%":[75],"fault":[78],"probabilities":[79],"compared":[80],"wire-length-minimum":[83],"layouts":[84],"for":[85],"circuits":[88],"which":[89],"have":[90],"up":[91],"14":[93],"transistors.":[94]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}