{"id":"https://openalex.org/W2158714394","doi":"https://doi.org/10.1109/isqed.2004.1283697","title":"Analytical dynamic time delay model of strongly coupled RLC interconnect lines dependent on switching","display_name":"Analytical dynamic time delay model of strongly coupled RLC interconnect lines dependent on switching","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W2158714394","doi":"https://doi.org/10.1109/isqed.2004.1283697","mag":"2158714394"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2004.1283697","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2004.1283697","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084426205","display_name":"Seongkyun Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Seongkyun Shin","raw_affiliation_strings":["Department of Electrical and computer Engineering, Hanyang University, Ansan, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and computer Engineering, Hanyang University, Ansan, Kyunggi, South Korea","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019499511","display_name":"Yungseon Eo","orcid":"https://orcid.org/0000-0003-3283-757X"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yungseon Eo","raw_affiliation_strings":["Department of Electrical and computer Engineering, Hanyang University, Ansan, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and computer Engineering, Hanyang University, Ansan, Kyunggi, South Korea","institution_ids":["https://openalex.org/I4575257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061760483","display_name":"W.R. Eisenstadt","orcid":"https://orcid.org/0000-0003-2920-6638"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.R. Eisenstadt","raw_affiliation_strings":["Department of Electrical and computer Engineering, University of Florida, Gainesville, FL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018382486","display_name":"Jong\u2010In Shim","orcid":"https://orcid.org/0000-0002-1305-074X"},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jongin Shim","raw_affiliation_strings":["Department of Electrical and computer Engineering, Hanyang University, Ansan, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and computer Engineering, Hanyang University, Ansan, Kyunggi, South Korea","institution_ids":["https://openalex.org/I4575257"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5084426205"],"corresponding_institution_ids":["https://openalex.org/I4575257"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18466866,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"21","issue":null,"first_page":"337","last_page":"342"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.8420488834381104},{"id":"https://openalex.org/keywords/rlc-circuit","display_name":"RLC circuit","score":0.8066719770431519},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.7659563422203064},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6191405057907104},{"id":"https://openalex.org/keywords/line","display_name":"Line (geometry)","score":0.5620837807655334},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5589479804039001},{"id":"https://openalex.org/keywords/transient","display_name":"Transient (computer programming)","score":0.5279666185379028},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.4997899532318115},{"id":"https://openalex.org/keywords/inductance","display_name":"Inductance","score":0.4824874699115753},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.45142096281051636},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4500857889652252},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44597649574279785},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.30160605907440186},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24185919761657715},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22090211510658264},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20002591609954834},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.18327432870864868},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.15449869632720947},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13224506378173828}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8420488834381104},{"id":"https://openalex.org/C89880566","wikidata":"https://www.wikidata.org/wiki/Q323477","display_name":"RLC circuit","level":4,"score":0.8066719770431519},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.7659563422203064},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6191405057907104},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.5620837807655334},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5589479804039001},{"id":"https://openalex.org/C2780799671","wikidata":"https://www.wikidata.org/wiki/Q17087362","display_name":"Transient (computer programming)","level":2,"score":0.5279666185379028},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.4997899532318115},{"id":"https://openalex.org/C29210110","wikidata":"https://www.wikidata.org/wiki/Q177897","display_name":"Inductance","level":3,"score":0.4824874699115753},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.45142096281051636},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4500857889652252},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44597649574279785},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.30160605907440186},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24185919761657715},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22090211510658264},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20002591609954834},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.18327432870864868},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.15449869632720947},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13224506378173828},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2004.1283697","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2004.1283697","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1858767651","https://openalex.org/W1990679103","https://openalex.org/W2009002210","https://openalex.org/W2025108824","https://openalex.org/W2066910438","https://openalex.org/W2108368155","https://openalex.org/W2116348324","https://openalex.org/W2118567051","https://openalex.org/W2121793199","https://openalex.org/W2127243000","https://openalex.org/W2142475299","https://openalex.org/W2144491528","https://openalex.org/W2162523242","https://openalex.org/W2165208933","https://openalex.org/W2165210723","https://openalex.org/W2166113800","https://openalex.org/W6684161441","https://openalex.org/W6684514280"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W1927636319","https://openalex.org/W2145535176","https://openalex.org/W3015599398","https://openalex.org/W2188730438","https://openalex.org/W2792778858","https://openalex.org/W2367816239","https://openalex.org/W4229446324","https://openalex.org/W2361185434","https://openalex.org/W2158805860"],"abstract_inverted_index":{"In":[0,22],"today's":[1],"UDSM(ultra-deep-sub-micron)-process-technology-based":[2],"ICs,":[3],"dynamic":[4],"delay":[5],"variations":[6],"of":[7,66],"strongly":[8],"coupled":[9,31],"lines":[10,32,42],"(due":[11],"to":[12,59],"neighboring":[13],"net":[14],"switching":[15,60],"activity)":[16],"make":[17],"static":[18],"timing":[19,27,89],"analysis":[20],"problematic.":[21],"this":[23],"paper,":[24],"new":[25],"analytical":[26,88],"models":[28,71,97],"for":[29,104],"RLC":[30],"are":[33,43,72],"presented":[34],"and":[35,55,118],"their":[36],"accuracy":[37],"is":[38,83,93],"verified.":[39],"Coupled":[40],"interconnect":[41],"decoupled":[44],"into":[45],"an":[46],"effective":[47,53,56,68],"single":[48,69,86],"line":[49,70,87,111,113],"model":[50,90],"by":[51,74,85],"using":[52],"capacitances":[54],"inductances":[57],"corresponding":[58],"activity.":[61],"Their":[62],"signal":[63],"transient":[64],"waveforms":[65],"the":[67,76,96],"determined":[73],"exploiting":[75],"TWA":[77],"(Traveling-wave-based":[78],"Waveform":[79],"Approximation)":[80],"technique.":[81],"This":[82],"followed":[84],"development.":[91],"It":[92],"shown":[94],"that":[95],"have":[98],"excellent":[99],"agreement":[100],"with":[101],"SPICE":[102],"simulations":[103],"various":[105],"circuit":[106],"performance":[107],"parameters":[108],"such":[109],"as":[110],"pitch,":[112],"length,":[114],"driver/receiver":[115],"size,":[116],"IMD-thickness,":[117],"aspect":[119],"ratio.":[120]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
