{"id":"https://openalex.org/W2141318245","doi":"https://doi.org/10.1109/isqed.2004.1283655","title":"Design for testability of FPGA blocks","display_name":"Design for testability of FPGA blocks","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W2141318245","doi":"https://doi.org/10.1109/isqed.2004.1283655","mag":"2141318245"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2004.1283655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2004.1283655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077157645","display_name":"Stuart McCracken","orcid":null},"institutions":[{"id":"https://openalex.org/I117023288","display_name":"Analog Devices (United States)","ror":"https://ror.org/01545pm61","country_code":"US","type":"company","lineage":["https://openalex.org/I117023288"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. McCracken","raw_affiliation_strings":["Analog Devices Inc.orporated, USA","[Analog Devices Inc.orporated, USA]"],"affiliations":[{"raw_affiliation_string":"Analog Devices Inc.orporated, USA","institution_ids":["https://openalex.org/I117023288"]},{"raw_affiliation_string":"[Analog Devices Inc.orporated, USA]","institution_ids":["https://openalex.org/I117023288"]}]},{"author_position":"last","author":{"id":null,"display_name":"Z. Zilic","orcid":null},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Z. Zilic","raw_affiliation_strings":["MACS Laboratory, McGill University, Canada","[MACS Laboratory, McGill University, Canada]"],"affiliations":[{"raw_affiliation_string":"MACS Laboratory, McGill University, Canada","institution_ids":["https://openalex.org/I5023651"]},{"raw_affiliation_string":"[MACS Laboratory, McGill University, Canada]","institution_ids":["https://openalex.org/I5023651"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5077157645"],"corresponding_institution_ids":["https://openalex.org/I117023288"],"apc_list":null,"apc_paid":null,"fwci":0.2728,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.5941391,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"86","last_page":"91"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.9365915060043335},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8064495325088501},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7978683114051819},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7959316372871399},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7037964463233948},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6555130481719971},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6384804844856262},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6289719939231873},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5906387567520142},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.540952742099762},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.5406655073165894},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.526132345199585},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5093151330947876},{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.4957598149776459},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.49566471576690674},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.45967912673950195},{"id":"https://openalex.org/keywords/device-under-test","display_name":"Device under test","score":0.4114006757736206},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4058235287666321},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2928431034088135},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.19717815518379211},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16841986775398254},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.1018018126487732}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.9365915060043335},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8064495325088501},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7978683114051819},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7959316372871399},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7037964463233948},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6555130481719971},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6384804844856262},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6289719939231873},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5906387567520142},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.540952742099762},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.5406655073165894},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.526132345199585},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5093151330947876},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.4957598149776459},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.49566471576690674},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.45967912673950195},{"id":"https://openalex.org/C76249512","wikidata":"https://www.wikidata.org/wiki/Q1206780","display_name":"Device under test","level":3,"score":0.4114006757736206},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4058235287666321},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2928431034088135},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.19717815518379211},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16841986775398254},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.1018018126487732},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C44838205","wikidata":"https://www.wikidata.org/wiki/Q127995","display_name":"Microwave","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2004.1283655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2004.1283655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1523051745","https://openalex.org/W1595368737","https://openalex.org/W1597088765","https://openalex.org/W1660562555","https://openalex.org/W2033047794","https://openalex.org/W2084641700","https://openalex.org/W2129183345","https://openalex.org/W2136537234","https://openalex.org/W2138530143","https://openalex.org/W2145643756","https://openalex.org/W2150098004","https://openalex.org/W2153887537","https://openalex.org/W2162529266","https://openalex.org/W2163865290","https://openalex.org/W2166478963","https://openalex.org/W4248869131","https://openalex.org/W4251533442","https://openalex.org/W4289127653","https://openalex.org/W6684360715"],"related_works":["https://openalex.org/W2184933991","https://openalex.org/W2123022840","https://openalex.org/W2761125259","https://openalex.org/W4288754393","https://openalex.org/W2117789795","https://openalex.org/W2104563825","https://openalex.org/W2154529098","https://openalex.org/W2105858357","https://openalex.org/W2061326683","https://openalex.org/W138400556"],"abstract_inverted_index":{"Reconfigurable":[0],"logic":[1],"devices":[2,16],"that":[3,27,90,121],"are":[4,10,17,98],"based":[5],"on":[6],"an":[7,119],"FPGA":[8,61,79],"substrate":[9],"gaining":[11],"widespread":[12],"acceptance.":[13],"As":[14],"such":[15],"used":[18],"in":[19],"many":[20],"different":[21],"configurations,":[22,113],"manufacturers":[23],"need":[24],"to":[25,35,41,49,52,67,100],"ensure":[26],"each":[28],"potential":[29],"configuration":[30,94],"will":[31],"not":[32],"fail":[33],"due":[34],"device":[36],"defects.":[37],"This":[38],"flexibility":[39],"leads":[40],"severely":[42],"increased":[43],"test":[44,55,70,75,82,102,105,112,124],"time.":[45],"We":[46,63],"show":[47],"how":[48],"use":[50],"reconfigurability":[51],"speed":[53],"up":[54],"and":[56,74,103,125],"diagnosis":[57,104,126],"times":[58,76],"of":[59,77,111,118,131],"individual":[60,78],"blocks.":[62,80],"present":[64],"a":[65,108],"scheme":[66],"incorporate":[68],"our":[69],"architecture,":[71],"reducing":[72],"diagnostic":[73],"The":[81],"architecture":[83],"includes":[84],"added":[85],"Feedback":[86],"Shift":[87],"Registers":[88],"(FSRs)":[89],"change":[91],"the":[92,116,123,132],"circuit":[93],"during":[95],"test.":[96],"Algorithms":[97],"presented":[99],"produce":[101],"sets":[106,127],"with":[107,115],"minimized":[109],"number":[110],"along":[114],"creation":[117],"FSR":[120],"produces":[122],"by":[128],"dynamic":[129],"reconfiguration":[130],"device.":[133]},"counts_by_year":[],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2025-10-10T00:00:00"}