{"id":"https://openalex.org/W1822414784","doi":"https://doi.org/10.1109/isqed.2003.1194719","title":"Design and use of memory-specific test structures to ensure SRAM yield and manufacturability","display_name":"Design and use of memory-specific test structures to ensure SRAM yield and manufacturability","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W1822414784","doi":"https://doi.org/10.1109/isqed.2003.1194719","mag":"1822414784"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2003.1194719","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2003.1194719","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072839897","display_name":"Franklin L. Duan","orcid":"https://orcid.org/0000-0003-1567-3673"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"F. Duan","raw_affiliation_strings":["LSI Logic Corporation, Milpitas, CA, USA","[LSI Logic Corporation, Milpitas, CA, USA]"],"affiliations":[{"raw_affiliation_string":"LSI Logic Corporation, Milpitas, CA, USA","institution_ids":[]},{"raw_affiliation_string":"[LSI Logic Corporation, Milpitas, CA, USA]","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062107205","display_name":"R. Castagnetti","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. Castagnetti","raw_affiliation_strings":["LSI Logic Corporation, Milpitas, CA, USA","[LSI Logic Corporation, Milpitas, CA, USA]"],"affiliations":[{"raw_affiliation_string":"LSI Logic Corporation, Milpitas, CA, USA","institution_ids":[]},{"raw_affiliation_string":"[LSI Logic Corporation, Milpitas, CA, USA]","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074449934","display_name":"R. Venkatraman","orcid":"https://orcid.org/0000-0003-4026-330X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. Venkatraman","raw_affiliation_strings":["LSI Logic Corporation, Milpitas, CA, USA","[LSI Logic Corporation, Milpitas, CA, USA]"],"affiliations":[{"raw_affiliation_string":"LSI Logic Corporation, Milpitas, CA, USA","institution_ids":[]},{"raw_affiliation_string":"[LSI Logic Corporation, Milpitas, CA, USA]","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081316305","display_name":"O. Kobozeva","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"O. Kobozeva","raw_affiliation_strings":["LSI Logic Corporation, Milpitas, CA, USA","[LSI Logic Corporation, Milpitas, CA, USA]"],"affiliations":[{"raw_affiliation_string":"LSI Logic Corporation, Milpitas, CA, USA","institution_ids":[]},{"raw_affiliation_string":"[LSI Logic Corporation, Milpitas, CA, USA]","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042000236","display_name":"S. Ramesh","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Ramesh","raw_affiliation_strings":["LSI Logic Corporation, Milpitas, CA, USA","[LSI Logic Corporation, Milpitas, CA, USA]"],"affiliations":[{"raw_affiliation_string":"LSI Logic Corporation, Milpitas, CA, USA","institution_ids":[]},{"raw_affiliation_string":"[LSI Logic Corporation, Milpitas, CA, USA]","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5072839897"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.7103,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.89278033,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"119","last_page":"124"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.950096845626831},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.9008121490478516},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5170734524726868},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47177791595458984},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45974260568618774},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.435099720954895},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4236270785331726},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.41894739866256714},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.40465953946113586},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3803900480270386},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19500821828842163},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1297757923603058}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.950096845626831},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.9008121490478516},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5170734524726868},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47177791595458984},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45974260568618774},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.435099720954895},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4236270785331726},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.41894739866256714},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.40465953946113586},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3803900480270386},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19500821828842163},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1297757923603058},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isqed.2003.1194719","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2003.1194719","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.409.218","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.409.218","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/isqed03/pdffiles/2b_1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1576717867","https://openalex.org/W2114929981","https://openalex.org/W2122201019","https://openalex.org/W2168963057","https://openalex.org/W3127686768","https://openalex.org/W6634626897"],"related_works":["https://openalex.org/W2094969048","https://openalex.org/W994558755","https://openalex.org/W3035935536","https://openalex.org/W2010746423","https://openalex.org/W2117710422","https://openalex.org/W2372119205","https://openalex.org/W1787300689","https://openalex.org/W4283270028","https://openalex.org/W1891369868","https://openalex.org/W2119025037"],"abstract_inverted_index":{"High-density":[0],"and":[1,4,22,44,50,55,65,88,97,112,121,160,164,197],"high-performance":[2],"single-port":[3],"dual-port":[5],"SRAM":[6,26,42,59,77,147,169,182],"increasingly":[7],"occupy":[8],"a":[9],"majority":[10],"of":[11,24,99,141,214],"the":[12,25,30,40,52,95,142,181,194,211,215],"chip":[13],"area":[14],"in":[15,61,146,185,210],"system-on-chip":[16],"product":[17],"designs.":[18],"Therefore,":[19],"good":[20,155],"yieldability":[21],"manufacturability":[23],"are":[27,79,218],"essential.":[28],"At":[29],"same":[31],"time":[32],"there":[33],"is":[34],"tremendous":[35],"competitive":[36],"pressure":[37],"to":[38,107,113,135,157,167,179,192],"get":[39],"best":[41],"density":[43,87],"performance.":[45,89],"We":[46,72,123,172],"have":[47,73,104,124,173],"previously":[48],"published":[49],"presented":[51],"industry's":[53],"smallest":[54],"fastest":[56],"embedded":[57],"6T":[58],"bitcells":[60,78],"0.18":[62],"/spl":[63],"mu/m":[64],"130":[66],"nm":[67],"generation":[68],"standard":[69],"CMOS":[70],"process.":[71],"described":[74],"how":[75],"these":[76,150],"robust":[80],"by":[81],"design":[82,96,117,145,204],"even":[83],"while":[84],"aggressively":[85],"driving":[86],"In":[90],"this":[91],"paper":[92],"we":[93],"discuss":[94],"use":[98],"SRAM-specific":[100,151],"test":[101,126,152,177],"structures":[102,127,153,178],"that":[103],"enabled":[105],"us":[106,166,199],"quickly":[108],"evaluate":[109,193],"process-design":[110],"interactions":[111],"fine-tune":[114],"process":[115,143],"and/or":[116],"for":[118,137,202,221],"improving":[119],"yields":[120,170],"manufacturability.":[122],"designed":[125,175],"using":[128],"our":[129],"aggressive":[130],"production":[131],"bitcell":[132],"as":[133],"basis":[134],"probe":[136],"any":[138],"possible":[139],"weaknesses":[140],"or":[144],"Results":[148,190],"from":[149],"show":[154],"correlation":[156],"yield":[158],"results":[159],"in-line":[161],"SEM":[162],"observations,":[163],"enable":[165],"improve":[168],"quickly.":[171],"also":[174,219],"SRAM-transistor":[176],"characterize":[180],"cell":[183],"devices":[184],"their":[186],"real":[187],"working":[188],"environment.":[189],"help":[191],"circuit":[195],"performance":[196],"provide":[198],"with":[200],"guidelines":[201],"further":[203],"improvements.":[205],"These":[206],"data":[207],"when":[208],"used":[209],"early":[212],"stage":[213],"development":[216],"cycle":[217],"useful":[220],"model":[222],"validation.":[223]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}