{"id":"https://openalex.org/W2076487538","doi":"https://doi.org/10.1109/ispass.2015.7095780","title":"DELPHI: a framework for RTL-based architecture design evaluation using DSENT models","display_name":"DELPHI: a framework for RTL-based architecture design evaluation using DSENT models","publication_year":2015,"publication_date":"2015-03-01","ids":{"openalex":"https://openalex.org/W2076487538","doi":"https://doi.org/10.1109/ispass.2015.7095780","mag":"2076487538"},"language":"en","primary_location":{"id":"doi:10.1109/ispass.2015.7095780","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2015.7095780","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069512237","display_name":"Michael Papamichael","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael K. Papamichael","raw_affiliation_strings":["Carnegie Mellon University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057222449","display_name":"Cagla Cakir","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cagla Cakir","raw_affiliation_strings":["Carnegie Mellon University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008961990","display_name":"Chen Suny Chia-Hsin","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chen Suny Chia-Hsin","raw_affiliation_strings":["Massachusetts Institute of Technology, Cambridge, MA, US","Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology, Cambridge, MA, US","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037775806","display_name":"Owen Cheny","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Owen Cheny","raw_affiliation_strings":["Massachusetts Institute of Technology, Cambridge, MA, US","Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology, Cambridge, MA, US","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110149045","display_name":"James C. Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James C. Ho","raw_affiliation_strings":["Massachusetts Institute of Technology, Cambridge, MA, US","Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology, Cambridge, MA, US","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000377660","display_name":"Ken Mai","orcid":"https://orcid.org/0000-0002-9096-8757"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ken Mai","raw_affiliation_strings":["Carnegie Mellon University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086114732","display_name":"Li-Shiuan Pehy","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li-Shiuan Pehy","raw_affiliation_strings":["Massachusetts Institute of Technology, Cambridge, MA, US","Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology, Cambridge, MA, US","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025438151","display_name":"Vladimir Stojanovi\u0107","orcid":"https://orcid.org/0000-0001-7233-6863"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vladimir Stojanovic","raw_affiliation_strings":["Univcrsity of California, Berkeley","University of California, Berkeley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univcrsity of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6589,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.70345423,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"11","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8639863133430481},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.740780234336853},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6333918571472168},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6295942664146423},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6033518314361572},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5837218165397644},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5053537487983704},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4919106960296631},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.485566109418869},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48358649015426636},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4780574142932892},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.46944260597229004},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.43074098229408264},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32573962211608887},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.32295435667037964},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.23649370670318604},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15064558386802673},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.13370266556739807},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12042981386184692},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.09906119108200073}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8639863133430481},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.740780234336853},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6333918571472168},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6295942664146423},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6033518314361572},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5837218165397644},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5053537487983704},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4919106960296631},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.485566109418869},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48358649015426636},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4780574142932892},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.46944260597229004},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.43074098229408264},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32573962211608887},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.32295435667037964},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.23649370670318604},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15064558386802673},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.13370266556739807},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12042981386184692},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.09906119108200073},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ispass.2015.7095780","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2015.7095780","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1966861321","https://openalex.org/W1976878754","https://openalex.org/W1985818188","https://openalex.org/W2015463653","https://openalex.org/W2102727118","https://openalex.org/W2128885449","https://openalex.org/W2138689074","https://openalex.org/W2157225945","https://openalex.org/W2161522487","https://openalex.org/W2166151045","https://openalex.org/W2170382128","https://openalex.org/W2464177207","https://openalex.org/W3140903683","https://openalex.org/W4232206474","https://openalex.org/W4236302577","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W4288055011","https://openalex.org/W2100360214","https://openalex.org/W1984090905","https://openalex.org/W2498204369","https://openalex.org/W4242912623","https://openalex.org/W4233602124","https://openalex.org/W2156965212","https://openalex.org/W2993028905","https://openalex.org/W2543290882","https://openalex.org/W2544421437"],"abstract_inverted_index":{"Computer":[0],"architects":[1],"are":[2,240],"increasingly":[3],"interested":[4],"in":[5],"evaluating":[6],"their":[7],"ideas":[8],"at":[9,251],"the":[10,20,32,46,97,123,143,165,234,242],"register-transfer":[11],"level":[12],"(RTL)":[13],"to":[14,83,135,147,168,172,221],"gain":[15],"more":[16,105],"precise":[17],"insights":[18],"on":[19],"key":[21],"characteristics":[22],"(frequency,":[23],"area,":[24,189],"power)":[25],"of":[26,48,50,108,132,164,175,182,195,228],"a":[27,51,91,115,130,149,161,193,247],"micro/architectural":[28],"design":[29,120,152,213,226],"proposal.":[30],"However,":[31],"RTL":[33,109,119,180,212,230],"synthesis":[34,231],"process":[35],"is":[36,43,71],"notoriously":[37],"tedious,":[38],"slow,":[39],"and":[40,42,65,79,104,190,216,224,237],"errorprone":[41],"often":[44],"outside":[45],"area":[47],"expertise":[49],"typical":[52],"computer":[53],"architect,":[54],"as":[55,187],"it":[56],"requires":[57],"familiarity":[58],"with":[59],"complex":[60],"CAD":[61],"flows,":[62],"hard-to-get":[63],"tools":[64],"standard":[66,80],"cell":[67,81],"libraries.":[68],"The":[69],"effort":[70],"further":[72],"multiplied":[73],"when":[74],"targeting":[75],"multiple":[76],"technology":[77,85,197],"nodes":[78],"variants":[82],"study":[84],"dependence.":[86],"This":[87,154],"paper":[88],"presents":[89],"DELPHI,":[90],"flexible,":[92],"open":[93],"framework":[94,245],"that":[95],"leverages":[96],"DSENT":[98,151,166,196,217],"modeling":[99],"engine":[100],"for":[101],"faster,":[102],"easier,":[103],"efficient":[106],"characterization":[107],"hardware":[110,183],"designs.":[111],"DELPHI":[112,215,244],"first":[113],"synthesizes":[114],"Verilog":[116],"or":[117,129],"VHDL":[118],"(either":[121],"using":[122,210],"industry-standard":[124],"Synopsys":[125],"Design":[126],"Compiler":[127],"tool":[128],"combination":[131],"open-source":[133,249],"tools)":[134],"an":[136],"intermediate":[137],"structural":[138],"netlist.":[139],"It":[140],"then":[141,157],"processes":[142],"resulting":[144],"synthesized":[145],"netlist":[146],"generate":[148],"technology-independent":[150],"model.":[153],"model":[155],"can":[156],"be":[158],"used":[159],"within":[160],"modified":[162],"version":[163],"flow":[167],"perform":[169],"very":[170],"fast\u2014one":[171],"two":[173],"orders":[174],"magnitude":[176],"faster":[177],"than":[178],"full":[179,243],"synthesis\u2014estimation":[181],"performance":[184],"characteristics,":[185],"such":[186],"frequency,":[188],"power":[191],"across":[192],"variety":[194],"models":[198],"(e.g.,":[199],"65nm":[200],"Bulk,":[201],"32nm":[202],"SOI,":[203],"11nm":[204],"Tri-Gate,":[205],"etc.).":[206],"In":[207],"our":[208],"evaluation":[209],"26":[211],"examples,":[214],"were":[218],"consistently":[219],"able":[220],"closely":[222],"track":[223],"capture":[225],"trends":[227],"conventional":[229],"results":[232],"without":[233],"associated":[235],"delay":[236],"complexity.":[238],"We":[239],"releasing":[241],"(including":[246],"fully":[248],"flow)":[250],"http://www.ece.cmu.edu/CALCM/delphi/.":[252]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
