{"id":"https://openalex.org/W2171674228","doi":"https://doi.org/10.1109/ispass.2013.6557152","title":"Evaluating cache coherent shared virtual memory for heterogeneous multicore chips","display_name":"Evaluating cache coherent shared virtual memory for heterogeneous multicore chips","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W2171674228","doi":"https://doi.org/10.1109/ispass.2013.6557152","mag":"2171674228"},"language":"en","primary_location":{"id":"doi:10.1109/ispass.2013.6557152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2013.6557152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005628986","display_name":"Blake A. Hechtman","orcid":null},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Blake A. Hechtman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Duke University, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Duke University, USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072847774","display_name":"Daniel J. Sorin","orcid":"https://orcid.org/0000-0001-7013-8986"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel J. Sorin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Duke University, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Duke University, USA","institution_ids":["https://openalex.org/I170897317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5005628986"],"corresponding_institution_ids":["https://openalex.org/I170897317"],"apc_list":null,"apc_paid":null,"fwci":3.4886,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.92886056,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"23","issue":null,"first_page":"118","last_page":"119"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8375946879386902},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6020245552062988},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5846095681190491},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5489268898963928},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.532191276550293},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5085910558700562},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.48615023493766785},{"id":"https://openalex.org/keywords/posix-threads","display_name":"POSIX Threads","score":0.4419954717159271},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4402892291545868},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.4101142883300781},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.390174925327301},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.28494760394096375},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24575772881507874},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.13123387098312378},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08537781238555908}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8375946879386902},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6020245552062988},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5846095681190491},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5489268898963928},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.532191276550293},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5085910558700562},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.48615023493766785},{"id":"https://openalex.org/C41138395","wikidata":"https://www.wikidata.org/wiki/Q928112","display_name":"POSIX Threads","level":3,"score":0.4419954717159271},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4402892291545868},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.4101142883300781},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.390174925327301},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.28494760394096375},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24575772881507874},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.13123387098312378},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08537781238555908}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ispass.2013.6557152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2013.6557152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5400000214576721,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320307769","display_name":"Astellas Pharma US","ror":"https://ror.org/05pw69n24"},{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1525350307","https://openalex.org/W1969646797","https://openalex.org/W1997352364","https://openalex.org/W2004937484","https://openalex.org/W2007432529","https://openalex.org/W2010802738","https://openalex.org/W2012252449","https://openalex.org/W2024122052","https://openalex.org/W2046996113","https://openalex.org/W2053063891","https://openalex.org/W2054739713","https://openalex.org/W2059807497","https://openalex.org/W2076264849","https://openalex.org/W2088032806","https://openalex.org/W2095894588","https://openalex.org/W2100011668","https://openalex.org/W2100415730","https://openalex.org/W2100893446","https://openalex.org/W2104345864","https://openalex.org/W2121758805","https://openalex.org/W2127945400","https://openalex.org/W2133654146","https://openalex.org/W2140643961","https://openalex.org/W2144008706","https://openalex.org/W2147657366","https://openalex.org/W2150722965","https://openalex.org/W2151460056","https://openalex.org/W2152484003","https://openalex.org/W2159481344","https://openalex.org/W2164391801","https://openalex.org/W2165039583","https://openalex.org/W2169150396","https://openalex.org/W2467941640","https://openalex.org/W2468944713","https://openalex.org/W2500686521","https://openalex.org/W2545500460","https://openalex.org/W6719873167"],"related_works":["https://openalex.org/W3148006657","https://openalex.org/W2006071227","https://openalex.org/W2140955407","https://openalex.org/W990235011","https://openalex.org/W4285144448","https://openalex.org/W2398725611","https://openalex.org/W2042087811","https://openalex.org/W2163552442","https://openalex.org/W2138782497","https://openalex.org/W18986865"],"abstract_inverted_index":{"Although":[0],"current":[1,23],"homogeneous":[2],"chips":[3],"tightly":[4],"couple":[5],"the":[6,17,44],"cores":[7],"with":[8],"cache-coherent":[9],"shared":[10],"virtual":[11],"memory":[12],"(CCSVM),":[13],"this":[14,27,50],"is":[15],"not":[16],"communication":[18,70],"paradigm":[19],"used":[20],"by":[21],"any":[22],"heterogeneous":[24],"chip.":[25],"In":[26],"paper,":[28],"we":[29],"present":[30],"a":[31,35,57],"CCSVM":[32],"design":[33],"for":[34,48],"CPU/GPU":[36,59],"chip,":[37],"as":[38,40],"well":[39],"an":[41],"extension":[42],"of":[43],"pthreads":[45],"programming":[46,49],"model":[47],"HMC.":[51],"We":[52],"experimentally":[53],"compare":[54],"CCSVM/xthreads":[55],"to":[56],"state-of-the-art":[58],"chip":[60],"from":[61],"AMD":[62],"that":[63],"runs":[64],"OpenCL":[65],"software.":[66],"CCSVM's":[67],"more":[68],"efficient":[69],"enables":[71],"far":[72,76],"better":[73],"performance":[74],"and":[75],"fewer":[77],"DRAM":[78],"accesses.":[79]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
