{"id":"https://openalex.org/W2146412446","doi":"https://doi.org/10.1109/ispass.2009.4919643","title":"CMPSched$im: Evaluating OS/CMP interaction on shared cache management","display_name":"CMPSched$im: Evaluating OS/CMP interaction on shared cache management","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W2146412446","doi":"https://doi.org/10.1109/ispass.2009.4919643","mag":"2146412446"},"language":"en","primary_location":{"id":"doi:10.1109/ispass.2009.4919643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2009.4919643","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041534663","display_name":"Jaideep Moses","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jaideep Moses","raw_affiliation_strings":["Hardware Architecture Laboratory, Intel Corporation, USA","[Hardware Architecture Laboratory, Intel Corporation, USA]"],"affiliations":[{"raw_affiliation_string":"Hardware Architecture Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Hardware Architecture Laboratory, Intel Corporation, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005170010","display_name":"Konstantinos Aisopos","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Konstantinos Aisopos","raw_affiliation_strings":["Hardware Architecture Laboratory, Intel Corporation, USA","Princeton University, USA"],"affiliations":[{"raw_affiliation_string":"Hardware Architecture Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Princeton University, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078825915","display_name":"Aamer Jaleel","orcid":"https://orcid.org/0000-0002-5709-2992"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aamer Jaleel","raw_affiliation_strings":["Hardware Architecture Laboratory, Intel Corporation, USA","[Hardware Architecture Laboratory, Intel Corporation, USA]"],"affiliations":[{"raw_affiliation_string":"Hardware Architecture Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Hardware Architecture Laboratory, Intel Corporation, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111987814","display_name":"Ravi Iyer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ravi Iyer","raw_affiliation_strings":["Hardware Architecture Laboratory, Intel Corporation, USA","[Hardware Architecture Laboratory, Intel Corporation, USA]"],"affiliations":[{"raw_affiliation_string":"Hardware Architecture Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Hardware Architecture Laboratory, Intel Corporation, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088669728","display_name":"Ramesh Illikkal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ramesh Illikkal","raw_affiliation_strings":["Hardware Architecture Laboratory, Intel Corporation, USA","[Hardware Architecture Laboratory, Intel Corporation, USA]"],"affiliations":[{"raw_affiliation_string":"Hardware Architecture Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Hardware Architecture Laboratory, Intel Corporation, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110280135","display_name":"Don Newell","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Don Newell","raw_affiliation_strings":["Hardware Architecture Laboratory, Intel Corporation, USA","[Hardware Architecture Laboratory, Intel Corporation, USA]"],"affiliations":[{"raw_affiliation_string":"Hardware Architecture Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Hardware Architecture Laboratory, Intel Corporation, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010737897","display_name":"Srihari Makineni","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srihari Makineni","raw_affiliation_strings":["Hardware Architecture Laboratory, Intel Corporation, USA","[Hardware Architecture Laboratory, Intel Corporation, USA]"],"affiliations":[{"raw_affiliation_string":"Hardware Architecture Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Hardware Architecture Laboratory, Intel Corporation, USA]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5041534663"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":3.7487,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.93775423,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"113","last_page":"122"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8702410459518433},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6427463293075562},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5627463459968567},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4363640248775482},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.43180084228515625},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.42447373270988464}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8702410459518433},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6427463293075562},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5627463459968567},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4363640248775482},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.43180084228515625},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.42447373270988464},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ispass.2009.4919643","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2009.4919643","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.207.9046","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.207.9046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.mit.edu/%7Ekaisopos/papers/CMPSched%24im_ISPASS_2009.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1998310976","https://openalex.org/W2010843180","https://openalex.org/W2014809728","https://openalex.org/W2103115317","https://openalex.org/W2117544540","https://openalex.org/W2129816520","https://openalex.org/W2136466435","https://openalex.org/W2143773524","https://openalex.org/W2147943147","https://openalex.org/W2155396321","https://openalex.org/W4244814458","https://openalex.org/W4247264372"],"related_works":["https://openalex.org/W2152099439","https://openalex.org/W1984163603","https://openalex.org/W2418291489","https://openalex.org/W3130422087","https://openalex.org/W3004195166","https://openalex.org/W2068121105","https://openalex.org/W1563139915","https://openalex.org/W4288413100","https://openalex.org/W2885669284","https://openalex.org/W4301184821"],"abstract_inverted_index":{"CMPs":[0],"have":[1],"now":[2],"become":[3],"mainstream":[4],"and":[5,19,50,59,87,111,118,139,152,192],"are":[6],"growing":[7],"in":[8,150,175,206],"complexity":[9],"with":[10],"more":[11],"cores,":[12],"several":[13],"shared":[14,101,171,208],"resources":[15],"(cache,":[16],"memory,":[17],"etc)":[18,49],"the":[20,38,41,51,83,100,126,176,202,207],"potential":[21],"for":[22],"additional":[23],"heterogeneous":[24],"elements.":[25],"In":[26,72,90,144],"order":[27],"to":[28,36,81,98,162,184,195],"manage":[29],"these":[30],"resources,":[31],"it":[32,65],"is":[33,62,93],"becoming":[34],"critical":[35],"optimize":[37,163],"interaction":[39,84,107,123],"between":[40,108],"execution":[42],"environment":[43],"(operating":[44],"systems,":[45],"virtual":[46],"machine":[47],"monitors,":[48],"CMP":[52,60,88,109,212],"platform.":[53,213],"Performance":[54],"analysis":[55],"of":[56,85,121,128,169,204,210],"such":[57],"OS":[58,86,164,181],"interactions":[61],"challenging":[63],"because":[64],"requires":[66],"long":[67],"running":[68],"full-system":[69],"execution-driven":[70],"simulations.":[71],"this":[73,122,145],"paper,":[74,146],"we":[75,147],"explore":[76],"an":[77],"alternative":[78],"approach":[79],"(CMPSched$im)":[80],"evaluate":[82],"architectures.":[89],"particular,":[91],"CMPSched$im":[92,115,149,158],"focused":[94],"on":[95],"evaluating":[96],"techniques":[97],"address":[99],"cache":[102,172,209],"management":[103],"problem":[104],"through":[105,189],"better":[106],"hardware":[110],"operating":[112],"system":[113,187],"scheduling.":[114],"enables":[116],"fast":[117],"flexible":[119],"exploration":[120],"by":[124,166],"combining":[125],"benefits":[127],"(a)":[129],"binary":[130],"instrumentation":[131],"tools":[132,137],"(Pin),":[133],"(b)":[134],"user-level":[135],"scheduling":[136,165,182,199],"(Linsched)":[138],"(c)":[140],"simple":[141],"core/cache":[142],"simulators.":[143],"describe":[148,180],"detail":[151],"present":[153],"case":[154],"studies":[155],"showing":[156],"how":[157],"can":[159],"be":[160],"used":[161],"taking":[167],"advantage":[168],"novel":[170],"monitoring":[173,191],"capabilities":[174],"hardware.":[177],"We":[178],"also":[179],"heuristics":[183],"improve":[185],"overall":[186],"performance":[188],"resource":[190],"application":[193],"classification":[194],"achieve":[196],"near":[197],"optimal":[198],"that":[200],"minimizes":[201],"effects":[203],"contention":[205],"a":[211]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":7}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}