{"id":"https://openalex.org/W2126112620","doi":"https://doi.org/10.1109/ispass.2009.4919638","title":"Zesto: A cycle-level simulator for highly detailed microarchitecture exploration","display_name":"Zesto: A cycle-level simulator for highly detailed microarchitecture exploration","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W2126112620","doi":"https://doi.org/10.1109/ispass.2009.4919638","mag":"2126112620"},"language":"en","primary_location":{"id":"doi:10.1109/ispass.2009.4919638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2009.4919638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102835155","display_name":"Gabriel H. Loh","orcid":"https://orcid.org/0000-0002-4616-0144"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Gabriel H. Loh","raw_affiliation_strings":["College of Computing, Georgia Institute of Technology, USA","Georgia Institute of Technology College of Computing, USA"],"affiliations":[{"raw_affiliation_string":"College of Computing, Georgia Institute of Technology, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Georgia Institute of Technology College of Computing, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004731389","display_name":"Samantika Subramaniam","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Samantika Subramaniam","raw_affiliation_strings":["College of Computing, Georgia Institute of Technology, USA","Georgia Institute of Technology College of Computing, USA"],"affiliations":[{"raw_affiliation_string":"College of Computing, Georgia Institute of Technology, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Georgia Institute of Technology College of Computing, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103416515","display_name":"Yuejian Xie","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuejian Xie","raw_affiliation_strings":["College of Computing, Georgia Institute of Technology, USA","Georgia Institute of Technology College of Computing, USA"],"affiliations":[{"raw_affiliation_string":"College of Computing, Georgia Institute of Technology, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Georgia Institute of Technology College of Computing, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5102835155"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":12.5848,"has_fulltext":false,"cited_by_count":123,"citation_normalized_percentile":{"value":0.98912118,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"53","last_page":"64"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.8719121217727661},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8579524159431458},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.6755625009536743},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.5927409529685974},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.554877758026123},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5537336468696594},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5152454972267151},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5015342235565186},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.4902632534503937},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.4897613525390625},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.48512229323387146},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"Speculative execution","score":0.43339404463768005},{"id":"https://openalex.org/keywords/microcode","display_name":"Microcode","score":0.43094372749328613},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3987120985984802},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2798359990119934},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1821707785129547}],"concepts":[{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.8719121217727661},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8579524159431458},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.6755625009536743},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.5927409529685974},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.554877758026123},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5537336468696594},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5152454972267151},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5015342235565186},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.4902632534503937},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.4897613525390625},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.48512229323387146},{"id":"https://openalex.org/C141331961","wikidata":"https://www.wikidata.org/wiki/Q2164465","display_name":"Speculative execution","level":2,"score":0.43339404463768005},{"id":"https://openalex.org/C22174128","wikidata":"https://www.wikidata.org/wiki/Q175869","display_name":"Microcode","level":2,"score":0.43094372749328613},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3987120985984802},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2798359990119934},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1821707785129547},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ispass.2009.4919638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2009.4919638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.157.1742","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.157.1742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www-static.cc.gatech.edu/~loh/Papers/ispass2009-zesto.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W198451133","https://openalex.org/W1510808677","https://openalex.org/W1980257390","https://openalex.org/W2035872164","https://openalex.org/W2044206819","https://openalex.org/W2104225326","https://openalex.org/W2113167168","https://openalex.org/W2115172404","https://openalex.org/W2117184662","https://openalex.org/W2118896605","https://openalex.org/W2119160628","https://openalex.org/W2124402026","https://openalex.org/W2127609451","https://openalex.org/W2134633067","https://openalex.org/W2141189134","https://openalex.org/W2159268023","https://openalex.org/W2164264749","https://openalex.org/W2545648915","https://openalex.org/W2626721396","https://openalex.org/W4236247894","https://openalex.org/W4239813889","https://openalex.org/W4239829442","https://openalex.org/W4244763500","https://openalex.org/W4247514140","https://openalex.org/W4248492382","https://openalex.org/W4253546582","https://openalex.org/W6602613798","https://openalex.org/W6608060382","https://openalex.org/W6677264922","https://openalex.org/W6738803852"],"related_works":["https://openalex.org/W2139338109","https://openalex.org/W2897302968","https://openalex.org/W2434762079","https://openalex.org/W2043979743","https://openalex.org/W1916582918","https://openalex.org/W37057355","https://openalex.org/W1595275176","https://openalex.org/W1584635396","https://openalex.org/W2150776253","https://openalex.org/W2085860917"],"abstract_inverted_index":{"For":[0,25,44],"academic":[1],"computer":[2],"architecture":[3],"research,":[4,47],"a":[5,38,86,92,97,113],"large":[6],"number":[7],"of":[8,14,21,28,58,80],"publicly":[9],"available":[10],"simulators":[11],"make":[12],"use":[13],"relatively":[15],"simple":[16,39,125],"abstractions":[17],"for":[18,33,136],"the":[19,22,55],"microarchitecture":[20,46,95,122],"processor":[23,82],"pipeline.":[24],"some":[26],"types":[27],"studies,":[29],"such":[30,48],"as":[31,49,117,119],"those":[32,50],"multi-core":[34],"cache":[35],"coherence":[36],"designs,":[37],"pipeline":[40],"model":[41,76],"may":[42],"suffice.":[43],"detailed":[45,114],"that":[51,90,106],"are":[52],"sensitive":[53],"to":[54],"exact":[56],"behavior":[57],"out-of-order":[59,102],"scheduling,":[60],"ALU":[61],"and":[62,66,71,104,131],"bypass":[63],"network":[64],"contention,":[65],"resource":[67],"management":[68],"(e.g.,":[69,124],"RS":[70],"ROB":[72],"entries),":[73],"an":[74],"over-simplified":[75],"is":[77],"not":[78],"representative":[79],"modern":[81,93],"organizations.":[83],"We":[84],"present":[85],"new":[87],"timing":[88],"simulator":[89],"models":[91],"x86":[94,138],"at":[96],"very":[98],"low":[99],"level,":[100],"including":[101],"scheduling":[103],"execution":[105],"much":[107],"more":[108],"closely":[109],"mirrors":[110],"current":[111],"implementations,":[112],"cache/memory":[115],"hierarchy,":[116],"well":[118],"many":[120],"x86-specific":[121],"features":[123],"vs.":[126],"complex":[127],"decoders,":[128],"micro-op":[129],"decomposition":[130],"fusion,":[132],"microcode":[133],"lookup":[134],"overhead":[135],"long/complex":[137],"instructions).":[139]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":15},{"year":2013,"cited_by_count":23},{"year":2012,"cited_by_count":18}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
