{"id":"https://openalex.org/W2157225945","doi":"https://doi.org/10.1109/ispass.2009.4919636","title":"GARNET: A detailed on-chip network model inside a full-system simulator","display_name":"GARNET: A detailed on-chip network model inside a full-system simulator","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W2157225945","doi":"https://doi.org/10.1109/ispass.2009.4919636","mag":"2157225945"},"language":"en","primary_location":{"id":"doi:10.1109/ispass.2009.4919636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2009.4919636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/1721.1/73506","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035320125","display_name":"Niket Agarwal","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Niket Agarwal","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034089074","display_name":"Tushar Krishna","orcid":"https://orcid.org/0000-0001-5738-6942"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tushar Krishna","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057413185","display_name":"Li-Shiuan Peh","orcid":"https://orcid.org/0000-0001-9010-6519"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li-Shiuan Peh","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086131079","display_name":"Niraj K. Jha","orcid":"https://orcid.org/0000-0002-1539-0369"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Niraj K. Jha","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5035320125"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":36.9799,"has_fulltext":false,"cited_by_count":753,"citation_normalized_percentile":{"value":0.99870475,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"33","last_page":"42"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6935274600982666},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6737010478973389},{"id":"https://openalex.org/keywords/uniprocessor-system","display_name":"Uniprocessor system","score":0.5595420002937317},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.5032777190208435},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.47448256611824036},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42840152978897095},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.41111689805984497},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3656606078147888},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.2533910870552063},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19460627436637878},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1723307967185974},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12359589338302612}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6935274600982666},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6737010478973389},{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.5595420002937317},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.5032777190208435},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.47448256611824036},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42840152978897095},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.41111689805984497},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3656606078147888},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.2533910870552063},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19460627436637878},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1723307967185974},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12359589338302612}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ispass.2009.4919636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2009.4919636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"},{"id":"pmh:oai:dspace.mit.edu:1721.1/73506","is_oa":true,"landing_page_url":"http://hdl.handle.net/1721.1/73506","pdf_url":null,"source":{"id":"https://openalex.org/S4306400425","display_name":"DSpace@MIT (Massachusetts Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I63966007","host_organization_name":"Massachusetts Institute of Technology","host_organization_lineage":["https://openalex.org/I63966007"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE","raw_type":"http://purl.org/eprint/type/ConferencePaper"}],"best_oa_location":{"id":"pmh:oai:dspace.mit.edu:1721.1/73506","is_oa":true,"landing_page_url":"http://hdl.handle.net/1721.1/73506","pdf_url":null,"source":{"id":"https://openalex.org/S4306400425","display_name":"DSpace@MIT (Massachusetts Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I63966007","host_organization_name":"Massachusetts Institute of Technology","host_organization_lineage":["https://openalex.org/I63966007"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE","raw_type":"http://purl.org/eprint/type/ConferencePaper"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W38543604","https://openalex.org/W1495578991","https://openalex.org/W1501077214","https://openalex.org/W1850405760","https://openalex.org/W1936682962","https://openalex.org/W2001505646","https://openalex.org/W2033797066","https://openalex.org/W2050336192","https://openalex.org/W2050487400","https://openalex.org/W2066162922","https://openalex.org/W2097117297","https://openalex.org/W2097560795","https://openalex.org/W2097876246","https://openalex.org/W2102387714","https://openalex.org/W2104225326","https://openalex.org/W2104674486","https://openalex.org/W2108783911","https://openalex.org/W2122337686","https://openalex.org/W2126372249","https://openalex.org/W2140064132","https://openalex.org/W2143515003","https://openalex.org/W2155597158","https://openalex.org/W2157569907","https://openalex.org/W2163061018","https://openalex.org/W2164264749","https://openalex.org/W4233412431","https://openalex.org/W4235990555","https://openalex.org/W4243278180","https://openalex.org/W4255387252","https://openalex.org/W4255469022","https://openalex.org/W4285719527","https://openalex.org/W6675224354","https://openalex.org/W6682888790"],"related_works":["https://openalex.org/W4297664933","https://openalex.org/W2145017421","https://openalex.org/W2068476500","https://openalex.org/W3198758847","https://openalex.org/W4230458348","https://openalex.org/W2033923590","https://openalex.org/W2517347894","https://openalex.org/W2576538540","https://openalex.org/W2376124569","https://openalex.org/W1581055755"],"abstract_inverted_index":{"Until":[0],"very":[1],"recently,":[2],"microprocessor":[3],"designs":[4,33],"were":[5],"computation-centric.":[6],"On-chip":[7],"communication":[8],"was":[9,13,23,239],"frequently":[10],"ignored.":[11],"This":[12,100],"because":[14],"of":[15,40,60,136,212,236],"fast,":[16],"single-cycle":[17],"on-chip":[18,48,274,288],"communication.":[19],"The":[20,234],"interconnect":[21,73,116,257],"power":[22,74],"also":[24,129,267],"insignificant":[25],"compared":[26],"to":[27,67,76,120,132,240,262,294],"the":[28,38,47,61,86,89,93,115,134,158,187,207,229,237,256,300],"transistor":[29,77],"power.":[30,78],"With":[31],"uniprocessor":[32],"providing":[34],"diminishing":[35],"returns":[36],"and":[37,72,92,104,186,199,209,218],"advent":[39],"chip":[41],"multiprocessors":[42],"(CMPs)":[43],"in":[44,258,279,286],"mainstream":[45],"systems,":[46],"network":[49,95,107,138,154,227,275,289],"that":[50,96,253,285],"connects":[51,97],"different":[52],"processing":[53],"cores":[54],"has":[55,65],"become":[56],"a":[57,102,110,125,150,165,197,216,223,248,280],"critical":[58],"part":[59],"design.":[62],"Transistor":[63],"miniaturization":[64],"led":[66],"high":[68],"global":[69],"wire":[70],"delay,":[71],"comparable":[75],"CMP":[79,126,221],"design":[80],"proposals":[81],"can":[82],"no":[83],"longer":[84],"ignore":[85],"interaction":[87],"between":[88],"memory":[90,201],"hierarchy":[91],"interconnection":[94,106,137,153,226],"various":[98],"elements.":[99],"necessitates":[101],"detailed":[103,151,198],"accurate":[105,200],"model":[108,155],"within":[109],"full-system":[111,160,281],"evaluation":[112,238],"framework.":[113,162],"Ignoring":[114],"details":[117],"might":[118,260],"lead":[119,261,293],"inaccurate":[121],"results":[122],"when":[123],"simulating":[124],"architecture.":[127],"It":[128],"becomes":[130],"important":[131],"analyze":[133],"impact":[135,211,301],"optimization":[139],"techniques":[140],"on":[141],"full":[142],"system":[143,202,297],"behavior.":[144],"In":[145],"this":[146],"light,":[147],"we":[148,214],"developed":[149],"cycle-accurate":[152],"(GARNET),":[156],"inside":[157],"GEMS":[159,231],"simulation":[161],"GARNET":[163],"models":[164],"classic":[166],"five-stage":[167],"pipelined":[168],"router":[169],"with":[170,194,222],"virtual":[171],"channel":[172],"(VC)":[173],"flow":[174,276],"control.":[175],"Microarchitectural":[176],"details,":[177],"such":[178],"as":[179],"flit-level":[180],"input":[181],"buffers,":[182],"routing":[183],"logic,":[184],"allocators":[185],"crossbar":[188],"switch,":[189],"are":[190],"modeled.":[191],"GARNET,":[192,213],"along":[193],"GEMS,":[195],"provides":[196],"timing":[203],"model.":[204],"To":[205],"demonstrate":[206],"importance":[208],"potential":[210],"evaluate":[215,268],"shared":[217],"private":[219],"L2":[220],"realistic":[224],"state-of-the-art":[225],"against":[228],"original":[230],"simple":[232],"network.":[233],"objective":[235],"figure":[241],"out":[242],"which":[243],"configuration":[244],"is":[245],"better":[246,295],"for":[247],"particular":[249],"workload.":[250],"We":[251,266,283],"show":[252,284],"not":[254],"modeling":[255],"detail":[259],"an":[263,273],"incorrect":[264],"outcome.":[265],"Express":[269],"Virtual":[270],"Channels":[271],"(EVCs),":[272],"control":[277],"proposal,":[278],"fashion.":[282],"improving":[287],"latency-throughput,":[290],"EVCs":[291],"do":[292],"overall":[296],"runtime,":[298],"however,":[299],"varies":[302],"widely":[303],"across":[304],"applications.":[305]},"counts_by_year":[{"year":2026,"cited_by_count":7},{"year":2025,"cited_by_count":29},{"year":2024,"cited_by_count":29},{"year":2023,"cited_by_count":27},{"year":2022,"cited_by_count":30},{"year":2021,"cited_by_count":49},{"year":2020,"cited_by_count":59},{"year":2019,"cited_by_count":42},{"year":2018,"cited_by_count":54},{"year":2017,"cited_by_count":64},{"year":2016,"cited_by_count":77},{"year":2015,"cited_by_count":68},{"year":2014,"cited_by_count":43},{"year":2013,"cited_by_count":72},{"year":2012,"cited_by_count":39}],"updated_date":"2026-04-07T14:57:38.498316","created_date":"2025-10-10T00:00:00"}