{"id":"https://openalex.org/W1936682962","doi":"https://doi.org/10.1109/ispass.2006.1620784","title":"RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform","display_name":"RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform","publication_year":2006,"publication_date":"2006-04-28","ids":{"openalex":"https://openalex.org/W1936682962","doi":"https://doi.org/10.1109/ispass.2006.1620784","mag":"1936682962"},"language":"en","primary_location":{"id":"doi:10.1109/ispass.2006.1620784","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2006.1620784","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101927146","display_name":"David A. Patterson","orcid":"https://orcid.org/0000-0002-0429-1015"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"D.A. Patterson","raw_affiliation_strings":["University of California, Berkeley, USA","California Univ., Berkeley, CA USA"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"California Univ., Berkeley, CA USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5101927146"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":8.9196,"has_fulltext":false,"cited_by_count":48,"citation_normalized_percentile":{"value":0.98432369,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7759485244750977},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6331367492675781},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5490666627883911},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.5278114080429077},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.49533572793006897},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.49319809675216675},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47991523146629333},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.47290050983428955},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4718078374862671},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4655054211616516},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.45372840762138367},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4270576238632202},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37172847986221313}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7759485244750977},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6331367492675781},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5490666627883911},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.5278114080429077},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.49533572793006897},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.49319809675216675},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47991523146629333},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.47290050983428955},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4718078374862671},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4655054211616516},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.45372840762138367},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4270576238632202},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37172847986221313},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ispass.2006.1620784","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispass.2006.1620784","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Performance Analysis of Systems and Software","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W150479808","https://openalex.org/W167281726","https://openalex.org/W1584744778","https://openalex.org/W1966708898","https://openalex.org/W1978507093","https://openalex.org/W2032094184","https://openalex.org/W2110612653","https://openalex.org/W2142449826","https://openalex.org/W2150053780","https://openalex.org/W2153456949","https://openalex.org/W2158924248","https://openalex.org/W2164264749"],"related_works":["https://openalex.org/W2154523322","https://openalex.org/W2083200807","https://openalex.org/W1603137082","https://openalex.org/W2364195017","https://openalex.org/W2355430452","https://openalex.org/W2049983405","https://openalex.org/W2392315374","https://openalex.org/W2094991910","https://openalex.org/W2326041751","https://openalex.org/W1970479385"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2,64],"given.":[3],"The":[4],"vast":[5],"majority":[6],"of":[7,13,20,119,157,234,312,316],"computer":[8,41,297,331],"architects":[9,158],"believe":[10,261],"the":[11,14,129,135,139,150,162,169,193,270,277,288,292,313,335],"future":[12,251],"microprocessor":[15],"is":[16,152,230],"hundreds":[17],"to":[18,36,55,78,160,203,214,224,290,302,307,325],"thousands":[19],"processors":[21,197],"(\"cores\")":[22],"on":[23,54,93],"a":[24,87,94,100,116,184,206,231,263,300,303,326],"chip.":[25],"Given":[26],"such":[27,262],"widespread":[28],"agreement,":[29],"it's":[30],"surprising":[31],"how":[32],"much":[33,322],"research":[34,191,267,333],"remains":[35],"be":[37,84,105,211],"done":[38],"in":[39,99,121,171,192,296,334],"algorithms,":[40],"architecture,":[42],"networks,":[43],"operating":[44,216],"systems,":[45,47],"file":[46],"compilers,":[48],"programming":[49],"languages,":[50],"applications,":[51],"and":[52,96,107,124,167,218,246,319],"so":[53,175,250],"realize":[56],"this":[57,112,165],"vision.":[58],"Fortunately,":[59],"Moore's":[60],"law":[61],"has":[62,70,287],"not":[63,187],"enabled":[65,72],"dense":[66,74],"multi-core":[67],"chips,":[68],"it":[69],"also":[71],"extremely":[73],"FPGAs.":[75],"Today,":[76],"one":[77],"two":[79],"dozen":[80],"soft":[81],"cores":[82,198,245],"can":[83,104,199],"programmed":[85],"into":[86],"single":[88],"FPGA.":[89],"With":[90],"multiple":[91,97,274,317],"FPGAs":[92,235],"board":[95],"boards":[98,143],"system,":[101],"1000-processor":[102],"designs":[103],"economically":[106],"rapidly":[108],"explored.":[109],"To":[110],"make":[111],"happen,":[113],"however,":[114],"requires":[115],"significant":[117],"amount":[118],"infrastructure":[120],"hardware,":[122],"software,":[123],"what":[125],"we":[126,260],"call":[127],"\"gateware\",":[128],"register-transfer":[130],"level":[131],"models":[132],"that":[133,144,176,272],"fill":[134],"FGPAs.":[136],"By":[137],"using":[138],"Berkeley":[140],"Emulation":[141],"Engine":[142],"were":[145],"created":[146],"for":[147,241,280,283,329],"other":[148],"purposes,":[149],"hardware":[151],"already":[153],"done.":[154],"A":[155],"group":[156],"plan":[159],"design":[161],"gateware,":[163],"create":[164],"infrastructure,":[166],"share":[168],"results":[170],"an":[172],"open-source":[173],"fashion":[174],"every":[177,236],"institution":[178],"could":[179],"have":[180],"their":[181],"own.":[182],"Such":[183],"system":[185,264],"would":[186,210,265],"just":[188],"invigorate":[189],"multiprocessors":[190],"architecture":[194],"community.":[195],"Since":[196],"run":[200,215,247],"at":[201,221],"100":[202],"200":[204],"MHz,":[205],"large":[207,219],"scale":[208],"multiprocessor":[209],"fast":[212],"enough":[213],"systems":[217,254,332],"programs":[220],"speeds":[222],"sufficient":[223],"support":[225],"software":[226],"research.":[227],"Moreover,":[228],"there":[229],"new":[232],"generation":[233],"18":[237],"months":[238],"with":[239],"capacity":[240],"twice":[242],"as":[243],"many":[244,314],"them":[248],"faster,":[249],"multiboard":[252],"FPGA":[253],"are":[255],"even":[256],"more":[257,323],"attractive.":[258],"Hence,":[259],"accelerate":[266],"across":[268,310],"all":[269],"fields":[271,315],"touch":[273],"processors.":[275],"Thus":[276],"acronynm":[278],"RAMP,":[279],"Research":[281],"Accelerator":[282],"Multiple":[284],"Processors.":[285],"RAMP":[286],"potential":[289],"transform":[291],"parallel":[293,327],"computing":[294],"community":[295],"science":[298],"from":[299],"simulation-driven":[301],"prototype-driven":[304],"discipline,":[305],"leading":[306],"rapid":[308],"iteration":[309],"interfaces":[311],"processors,":[318],"thereby":[320],"moving":[321],"quickly":[324],"foundation":[328],"large-scale":[330],"21st":[336],"century.":[337]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}