{"id":"https://openalex.org/W2096094746","doi":"https://doi.org/10.1109/ispan.2004.1300478","title":"Optimal loop scheduling with register constraints using flow graphs","display_name":"Optimal loop scheduling with register constraints using flow graphs","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2096094746","doi":"https://doi.org/10.1109/ispan.2004.1300478","mag":"2096094746"},"language":"en","primary_location":{"id":"doi:10.1109/ispan.2004.1300478","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispan.2004.1300478","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"7th International Symposium on Parallel Architectures, Algorithms and Networks, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033951881","display_name":"Jan M\u00fcller","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"J. Muller","raw_affiliation_strings":["Department of Electrical Engineering, Dresden University of Technology, Dresden, Germany","Dept. of Electr. Eng., Dresden Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Dresden University of Technology, Dresden, Germany","institution_ids":[]},{"raw_affiliation_string":"Dept. of Electr. Eng., Dresden Univ. of Technol., Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008284452","display_name":"Dirk Fimmel","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"D. Fimmel","raw_affiliation_strings":["Department of Electrical Engineering, Dresden University of Technology, Dresden, Germany","Dept. of Electr. Eng., Dresden Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Dresden University of Technology, Dresden, Germany","institution_ids":[]},{"raw_affiliation_string":"Dept. of Electr. Eng., Dresden Univ. of Technol., Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007941239","display_name":"Renate Merker","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Merker","raw_affiliation_strings":["Department of Electrical Engineering, Dresden University of Technology, Dresden, Germany","Dept. of Electr. Eng., Dresden Univ. of Technol., Germany"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Dresden University of Technology, Dresden, Germany","institution_ids":[]},{"raw_affiliation_string":"Dept. of Electr. Eng., Dresden Univ. of Technol., Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5033951881"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":1.5798,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.82565575,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"e86 d","issue":null,"first_page":"180","last_page":"185"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.7622652649879456},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7438091039657593},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5588377118110657},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5512387752532959},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49796438217163086},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.48188096284866333},{"id":"https://openalex.org/keywords/nested-loop-join","display_name":"Nested loop join","score":0.4557778835296631},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.45109933614730835},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.4249926507472992},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4114886522293091},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.35638323426246643},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1591198742389679},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10548332333564758}],"concepts":[{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.7622652649879456},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7438091039657593},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5588377118110657},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5512387752532959},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49796438217163086},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.48188096284866333},{"id":"https://openalex.org/C1306188","wikidata":"https://www.wikidata.org/wiki/Q4060687","display_name":"Nested loop join","level":2,"score":0.4557778835296631},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.45109933614730835},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.4249926507472992},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4114886522293091},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.35638323426246643},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1591198742389679},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10548332333564758},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ispan.2004.1300478","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispan.2004.1300478","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"7th International Symposium on Parallel Architectures, Algorithms and Networks, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W75728630","https://openalex.org/W90084074","https://openalex.org/W1515662025","https://openalex.org/W1572285379","https://openalex.org/W1591740858","https://openalex.org/W1883726693","https://openalex.org/W1963527085","https://openalex.org/W1972580129","https://openalex.org/W2053381804","https://openalex.org/W2106473597","https://openalex.org/W2113679613","https://openalex.org/W2119773132","https://openalex.org/W2119881593","https://openalex.org/W2133520239","https://openalex.org/W2157758640","https://openalex.org/W2296760900","https://openalex.org/W2708504258","https://openalex.org/W3001659479","https://openalex.org/W3148529197","https://openalex.org/W4232919122","https://openalex.org/W4255085755","https://openalex.org/W6603075439","https://openalex.org/W6631111002","https://openalex.org/W6633986733","https://openalex.org/W6679474086","https://openalex.org/W6740065049","https://openalex.org/W6773698162"],"related_works":["https://openalex.org/W1776429635","https://openalex.org/W154155438","https://openalex.org/W4205359103","https://openalex.org/W2481821631","https://openalex.org/W2058764256","https://openalex.org/W2114948246","https://openalex.org/W59945861","https://openalex.org/W2052992886","https://openalex.org/W1607259217","https://openalex.org/W2117007419"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,8,22,48,59],"novel":[3],"loop":[4,37,90],"scheduling":[5],"approach":[6,64],"using":[7],"generalized":[9],"flow":[10,24],"graph":[11,25],"model":[12,19],"of":[13],"the":[14,40,53,63,77,81],"resource":[15],"constraints.":[16,29],"From":[17],"this":[18],"we":[20],"derive":[21],"new":[23],"to":[26,74],"incorporate":[27],"register":[28],"Our":[30],"linear":[31],"programming":[32],"implementation":[33],"produces":[34],"an":[35],"optimum":[36],"schedule,":[38],"respecting":[39],"constraints":[41],"on":[42],"functional":[43,71],"units":[44],"and":[45,62,69,84,87],"registers":[46],"in":[47],"single":[49],"optimization":[50],"problem.":[51],"Moreover,":[52],"iteration":[54],"interval":[55],"is":[56],"treated":[57],"as":[58],"rational":[60],"number,":[61],"supports":[65],"heterogeneous":[66],"processor":[67],"architectures":[68],"pipelined":[70],"units.":[72],"Compared":[73],"earlier":[75],"approaches,":[76],"solution":[78,85],"can":[79],"reduce":[80],"problem":[82],"complexity":[83],"time,":[86],"provide":[88],"faster":[89],"schedules.":[91]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
