{"id":"https://openalex.org/W1999112322","doi":"https://doi.org/10.1109/ispacs.2013.6704574","title":"A new winner-take-all neural network using DPLL and phase modulated signal","display_name":"A new winner-take-all neural network using DPLL and phase modulated signal","publication_year":2013,"publication_date":"2013-11-01","ids":{"openalex":"https://openalex.org/W1999112322","doi":"https://doi.org/10.1109/ispacs.2013.6704574","mag":"1999112322"},"language":"en","primary_location":{"id":"doi:10.1109/ispacs.2013.6704574","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispacs.2013.6704574","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium on Intelligent Signal Processing and Communication Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050879589","display_name":"Masaki Azuma","orcid":null},"institutions":[{"id":"https://openalex.org/I56624758","display_name":"Kansai University","ror":"https://ror.org/03xg1f311","country_code":"JP","type":"education","lineage":["https://openalex.org/I56624758"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Masaki Azuma","raw_affiliation_strings":["Graduate School of Science and Engineering, Kansai University, Osaka, Japan","Grad. School of Sci. and Eng., Kansai University, Suita, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Engineering, Kansai University, Osaka, Japan","institution_ids":["https://openalex.org/I56624758"]},{"raw_affiliation_string":"Grad. School of Sci. and Eng., Kansai University, Suita, Japan","institution_ids":["https://openalex.org/I56624758"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030372589","display_name":"Hiroomi Hikawa","orcid":"https://orcid.org/0000-0003-2609-3500"},"institutions":[{"id":"https://openalex.org/I56624758","display_name":"Kansai University","ror":"https://ror.org/03xg1f311","country_code":"JP","type":"education","lineage":["https://openalex.org/I56624758"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroomi Hikawa","raw_affiliation_strings":["Graduate School of Science and Engineering, Kansai University, Osaka, Japan","Grad. School of Sci. and Eng., Kansai University, Suita, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Engineering, Kansai University, Osaka, Japan","institution_ids":["https://openalex.org/I56624758"]},{"raw_affiliation_string":"Grad. School of Sci. and Eng., Kansai University, Suita, Japan","institution_ids":["https://openalex.org/I56624758"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5050879589"],"corresponding_institution_ids":["https://openalex.org/I56624758"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07089001,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"105","issue":null,"first_page":"345","last_page":"350"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10232","display_name":"Optical Network Technologies","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.870408833026886},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7476004362106323},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.727328896522522},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.6658079028129578},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5458363890647888},{"id":"https://openalex.org/keywords/winner-take-all","display_name":"Winner-take-all","score":0.5294919610023499},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.5220175385475159},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5034837126731873},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41267532110214233},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.36569535732269287},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.36120346188545227},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33262068033218384},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32759416103363037},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25705066323280334},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15464845299720764},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08580067753791809}],"concepts":[{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.870408833026886},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7476004362106323},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.727328896522522},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.6658079028129578},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5458363890647888},{"id":"https://openalex.org/C168976158","wikidata":"https://www.wikidata.org/wiki/Q769931","display_name":"Winner-take-all","level":3,"score":0.5294919610023499},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.5220175385475159},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5034837126731873},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41267532110214233},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.36569535732269287},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.36120346188545227},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33262068033218384},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32759416103363037},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25705066323280334},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15464845299720764},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08580067753791809},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ispacs.2013.6704574","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ispacs.2013.6704574","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium on Intelligent Signal Processing and Communication Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1983417029","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W2378072250","https://openalex.org/W2103754166","https://openalex.org/W2043945969","https://openalex.org/W2082469970","https://openalex.org/W2058003010","https://openalex.org/W1994059163","https://openalex.org/W3113661469"],"abstract_inverted_index":{"Due":[0],"to":[1,97],"superior":[2],"learning":[3,109],"ability,":[4],"neural":[5,19],"network":[6,20],"is":[7,64,73,80],"widely":[8],"used":[9],"in":[10],"various":[11],"fields.":[12],"This":[13],"paper":[14],"proposes":[15],"a":[16,24,43],"hardware":[17],"winner-take-all":[18,26],"(WTANN)":[21],"which":[22],"has":[23,107],"new":[25],"(WTA)":[27],"circuit":[28,86],"with":[29,66],"phase-modulated":[30],"pulse":[31],"signal":[32],"and":[33,77,88],"digital":[34],"phase-locked":[35],"loops":[36],"(DPLLs).":[37],"The":[38,69],"system":[39],"uses":[40],"DPLL":[41],"as":[42],"computing":[44],"element,":[45],"so":[46],"all":[47],"input":[48],"values":[49],"are":[50,90],"expressed":[51],"by":[52,75,82,92],"phases":[53],"of":[54],"rectangular":[55],"signals.":[56],"In":[57],"hardwareWTANN,":[58],"the":[59,94,104],"proposed":[60,70,105],"winner":[61],"search":[62],"method":[63],"implemented":[65],"simple":[67],"circuit.":[68],"WTANN":[71,106],"architecture":[72],"described":[74],"VHDL":[76,95],"its":[78,85],"feasibility":[79],"verified":[81],"simulation.":[83],"Then":[84],"size":[87],"speed":[89],"evaluated":[91],"applying":[93],"description":[96],"logic":[98],"synthesis":[99],"tool.":[100],"Results":[101],"show":[102],"that":[103],"valid":[108],"characteristics.":[110]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}