{"id":"https://openalex.org/W2065759842","doi":"https://doi.org/10.1109/isorc.2013.6913224","title":"An SDRAM controller for real-time systems","display_name":"An SDRAM controller for real-time systems","publication_year":2013,"publication_date":"2013-06-01","ids":{"openalex":"https://openalex.org/W2065759842","doi":"https://doi.org/10.1109/isorc.2013.6913224","mag":"2065759842"},"language":"en","primary_location":{"id":"doi:10.1109/isorc.2013.6913224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isorc.2013.6913224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://orbit.dtu.dk/en/publications/ff63b6a9-2f26-44ca-936c-bd329c47670b","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041609247","display_name":"Edgar Lakis","orcid":null},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":true,"raw_author_name":"Edgar Lakis","raw_affiliation_strings":["Department of Applied Mathematics and Computer Science, Technical University of Denmark","Department of Applied Mathematics and Computer Science Technical University of Denmark"],"affiliations":[{"raw_affiliation_string":"Department of Applied Mathematics and Computer Science, Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"Department of Applied Mathematics and Computer Science Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083205602","display_name":"Martin Schoeberl","orcid":"https://orcid.org/0000-0003-2366-382X"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Martin Schoeberl","raw_affiliation_strings":["Department of Applied Mathematics and Computer Science, Technical University of Denmark","Department of Applied Mathematics and Computer Science Technical University of Denmark"],"affiliations":[{"raw_affiliation_string":"Department of Applied Mathematics and Computer Science, Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"Department of Applied Mathematics and Computer Science Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5041609247"],"corresponding_institution_ids":["https://openalex.org/I96673099"],"apc_list":null,"apc_paid":null,"fwci":2.22,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.87994143,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.863330602645874},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8415199518203735},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.8064670562744141},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6754132509231567},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6648017168045044},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6116288900375366},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5787304639816284},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5625637769699097},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4932484030723572},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.45121362805366516},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.44193312525749207},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.4307533800601959},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.42678046226501465},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.35677555203437805},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.33997637033462524},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3059026002883911},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25384584069252014},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.19567319750785828},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.17733356356620789},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.1118389368057251}],"concepts":[{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.863330602645874},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8415199518203735},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.8064670562744141},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6754132509231567},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6648017168045044},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6116288900375366},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5787304639816284},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5625637769699097},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4932484030723572},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.45121362805366516},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.44193312525749207},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.4307533800601959},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.42678046226501465},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.35677555203437805},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.33997637033462524},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3059026002883911},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25384584069252014},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.19567319750785828},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.17733356356620789},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.1118389368057251},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/isorc.2013.6913224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isorc.2013.6913224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.299.2170","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.2170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.jopdesign.com/doc/sdramctrl.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:publications/ff63b6a9-2f26-44ca-936c-bd329c47670b","is_oa":true,"landing_page_url":"https://orbit.dtu.dk/en/publications/ff63b6a9-2f26-44ca-936c-bd329c47670b","pdf_url":null,"source":{"id":"https://openalex.org/S4306400705","display_name":"Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I96673099","host_organization_name":"Technical University of Denmark","host_organization_lineage":["https://openalex.org/I96673099"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Lakis , E & Schoeberl , M 2013 , An SDRAM controller for real-time systems . in 2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) . IEEE , 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC , Paderborn , Germany , 19/06/2013 . https://doi.org/10.1109/ISORC.2013.6913224","raw_type":"contributionToPeriodical"}],"best_oa_location":{"id":"pmh:oai:pure.atira.dk:publications/ff63b6a9-2f26-44ca-936c-bd329c47670b","is_oa":true,"landing_page_url":"https://orbit.dtu.dk/en/publications/ff63b6a9-2f26-44ca-936c-bd329c47670b","pdf_url":null,"source":{"id":"https://openalex.org/S4306400705","display_name":"Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I96673099","host_organization_name":"Technical University of Denmark","host_organization_lineage":["https://openalex.org/I96673099"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Lakis , E & Schoeberl , M 2013 , An SDRAM controller for real-time systems . in 2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) . IEEE , 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC , Paderborn , Germany , 19/06/2013 . https://doi.org/10.1109/ISORC.2013.6913224","raw_type":"contributionToPeriodical"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W1554331127","https://openalex.org/W1715210439","https://openalex.org/W1976014094","https://openalex.org/W2012999152","https://openalex.org/W2066744234","https://openalex.org/W2085481531","https://openalex.org/W2095712519","https://openalex.org/W2102800454","https://openalex.org/W2116826559","https://openalex.org/W2151653149","https://openalex.org/W2165683591","https://openalex.org/W2256968453","https://openalex.org/W3023392404","https://openalex.org/W4285719527","https://openalex.org/W6637518700","https://openalex.org/W6776953718"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2896161911","https://openalex.org/W2185658074","https://openalex.org/W2065759842","https://openalex.org/W2019238062","https://openalex.org/W1707075782","https://openalex.org/W4393076761","https://openalex.org/W4289383899","https://openalex.org/W1725472669","https://openalex.org/W2138825797"],"abstract_inverted_index":{"For":[0],"real-time":[1],"systems":[2],"we":[3,117],"need":[4,53,82],"to":[5,14,29,54,83,86,98,136],"statically":[6],"determine":[7],"worst-case":[8],"execution":[9],"times":[10],"(WCET)":[11],"of":[12,18,107,140],"tasks":[13],"proof":[15],"the":[16,19,26,35,37,39,42,46,105,130,141],"schedulability":[17],"system.":[20],"To":[21],"enable":[22],"static":[23],"WCET":[24],"analysis,":[25],"platform":[27,33],"needs":[28],"be":[30,55,84],"time-predictable.":[31],"The":[32,125],"includes":[34],"processor,":[36],"caches,":[38],"memory":[40,91,112,142],"system,":[41,44],"operating":[43],"and":[45,80,133],"application":[47],"software":[48],"itself.":[49],"All":[50],"those":[51],"components":[52],"timing":[56,73],"analyzable.":[57],"Current":[58],"computers":[59],"use":[60],"DRAM":[61,70,94],"as":[62],"a":[63,138],"cost":[64,106],"effective":[65],"main":[66],"memory.":[67],"However,":[68],"these":[69],"chips":[71],"have":[72],"requirements":[74],"that":[75],"depend":[76],"on":[77],"former":[78],"accesses":[79],"also":[81],"refreshed":[85],"retain":[87],"their":[88],"content.":[89],"Standard":[90],"controllers":[92],"for":[93,110,122,129,144],"memories":[95],"are":[96],"optimized":[97,128],"provide":[99,137],"maximum":[100],"bandwidth":[101],"or":[102],"throughput":[103],"at":[104],"variable":[108],"latency":[109,135],"individual":[111],"accesses.":[113],"In":[114],"this":[115],"paper":[116],"present":[118],"an":[119],"SDRAM":[120],"controller":[121,126],"realtime":[123],"systems.":[124,146],"is":[127],"worst":[131],"case":[132],"constant":[134],"base":[139],"hierarchy":[143],"time-predictable":[145]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}