{"id":"https://openalex.org/W4404849676","doi":"https://doi.org/10.1109/isocc62682.2024.10762636","title":"SoC Platform for Heterogeneous Accelerator IPs SoC development platform for evaluation and demonstration","display_name":"SoC Platform for Heterogeneous Accelerator IPs SoC development platform for evaluation and demonstration","publication_year":2024,"publication_date":"2024-08-19","ids":{"openalex":"https://openalex.org/W4404849676","doi":"https://doi.org/10.1109/isocc62682.2024.10762636"},"language":"en","primary_location":{"id":"doi:10.1109/isocc62682.2024.10762636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc62682.2024.10762636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 21st International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001753397","display_name":"Atsushi Hasegawa","orcid":"https://orcid.org/0000-0002-7676-5929"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Atsushi Hasegawa","raw_affiliation_strings":["The University of Tokyo,Systems Design Lab.,Tokyo,Japan"],"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Systems Design Lab.,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089203206","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0003-0445-0167"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["The University of Tokyo,Systems Design Lab.,Tokyo,Japan"],"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Systems Design Lab.,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060263447","display_name":"Ichiro Naka","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ichiro Naka","raw_affiliation_strings":["AIST,Semiconductor Frontier Research Center,Tsukuba,Japan"],"affiliations":[{"raw_affiliation_string":"AIST,Semiconductor Frontier Research Center,Tsukuba,Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111998768","display_name":"Kunio Uchiyama","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kunio Uchiyama","raw_affiliation_strings":["AIST,Semiconductor Frontier Research Center,Tsukuba,Japan"],"affiliations":[{"raw_affiliation_string":"AIST,Semiconductor Frontier Research Center,Tsukuba,Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5001753397"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.5139,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66953915,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"191","last_page":"192"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6434229612350464},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5219385027885437},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5046716928482056},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4119284451007843},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.37633681297302246}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6434229612350464},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5219385027885437},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5046716928482056},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4119284451007843},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.37633681297302246}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc62682.2024.10762636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc62682.2024.10762636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 21st International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.41999998688697815,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337495","display_name":"Technology Development","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1550799777","https://openalex.org/W2107029536","https://openalex.org/W2130994398","https://openalex.org/W4365801665","https://openalex.org/W6847552951"],"related_works":["https://openalex.org/W2036806516","https://openalex.org/W1967394420","https://openalex.org/W2565425548","https://openalex.org/W2392009442","https://openalex.org/W2087695844","https://openalex.org/W2154106283","https://openalex.org/W2912613323","https://openalex.org/W2142443274","https://openalex.org/W3142211975","https://openalex.org/W2353292666"],"abstract_inverted_index":{"developed":[0],"SoC":[1],"Platform":[2],"and":[3,26],"design":[4],"methodology":[5],"for":[6,13],"Domain":[7],"Specific":[8],"Architecture":[9],"(DSA)":[10],"accelerator":[11],"IPs":[12],"two":[14],"process":[15],"technology.":[16],"Implemented":[17],"SoCs,":[18],"which":[19],"includes":[20],"multiple":[21],"AI":[22],"accelerators,":[23],"are":[24],"manufactured":[25],"evaluated":[27],"successfully.":[28]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-03-06T13:50:29.536080","created_date":"2025-10-10T00:00:00"}