{"id":"https://openalex.org/W3215101624","doi":"https://doi.org/10.1109/isocc53507.2021.9613922","title":"An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs)","display_name":"An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs)","publication_year":2021,"publication_date":"2021-10-06","ids":{"openalex":"https://openalex.org/W3215101624","doi":"https://doi.org/10.1109/isocc53507.2021.9613922","mag":"3215101624"},"language":"en","primary_location":{"id":"doi:10.1109/isocc53507.2021.9613922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc53507.2021.9613922","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 18th International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084427876","display_name":"Eunbin Park","orcid":"https://orcid.org/0000-0003-1380-7076"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Eunbin Park","raw_affiliation_strings":["School of Electronics Engineering, Kyungpook National University, Daegu, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, Kyungpook National University, Daegu, South Korea","institution_ids":["https://openalex.org/I31419693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032455044","display_name":"Taigon Song","orcid":"https://orcid.org/0000-0001-5243-4132"},"institutions":[{"id":"https://openalex.org/I31419693","display_name":"Kyungpook National University","ror":"https://ror.org/040c17130","country_code":"KR","type":"education","lineage":["https://openalex.org/I31419693"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taigon Song","raw_affiliation_strings":["School of Electronics Engineering, School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South Korea","institution_ids":["https://openalex.org/I31419693"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I31419693"],"apc_list":null,"apc_paid":null,"fwci":1.221,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.76857166,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"395","last_page":"396"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10361","display_name":"Silicon Carbide Semiconductor Technologies","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.9725088477134705},{"id":"https://openalex.org/keywords/parasitic-capacitance","display_name":"Parasitic capacitance","score":0.703490138053894},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.6658216714859009},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5457368493080139},{"id":"https://openalex.org/keywords/parasitic-element","display_name":"Parasitic element","score":0.5312324166297913},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4824538826942444},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45491552352905273},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4419122040271759},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3284945487976074},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2702890634536743},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.20588421821594238},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1625833809375763}],"concepts":[{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.9725088477134705},{"id":"https://openalex.org/C154318817","wikidata":"https://www.wikidata.org/wiki/Q2157249","display_name":"Parasitic capacitance","level":4,"score":0.703490138053894},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.6658216714859009},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5457368493080139},{"id":"https://openalex.org/C71367568","wikidata":"https://www.wikidata.org/wiki/Q3363655","display_name":"Parasitic element","level":2,"score":0.5312324166297913},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4824538826942444},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45491552352905273},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4419122040271759},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3284945487976074},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2702890634536743},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.20588421821594238},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1625833809375763},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc53507.2021.9613922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc53507.2021.9613922","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 18th International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322120","display_name":"National Research Foundation of Korea","ror":"https://ror.org/013aysd81"},{"id":"https://openalex.org/F4320326288","display_name":"K2","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2899004836","https://openalex.org/W2921386757","https://openalex.org/W2965234963","https://openalex.org/W3095098915","https://openalex.org/W3102668149","https://openalex.org/W3112123566"],"related_works":["https://openalex.org/W4385420419","https://openalex.org/W2147937468","https://openalex.org/W3135452629","https://openalex.org/W2156642062","https://openalex.org/W2164767665","https://openalex.org/W2188197907","https://openalex.org/W2770395904","https://openalex.org/W2131659205","https://openalex.org/W4246148806","https://openalex.org/W2782214096"],"abstract_inverted_index":{"The":[0],"Complementary":[1],"FET":[2],"(CFET)":[3],"is":[4,44],"known":[5],"to":[6,11,51,70,82],"be":[7],"a":[8,59],"potential":[9],"device":[10],"continue":[12],"the":[13,25,64,92],"feature":[14],"size":[15],"scaling.":[16],"However,":[17],"studies":[18],"forecast":[19],"that":[20,29,39,46,62],"increased":[21],"parasitic":[22],"RC":[23,40],"neutralizes":[24],"area":[26],"reduction":[27],"advantage":[28],"CFETs":[30,43],"can":[31],"provide.":[32],"In":[33],"this":[34,72],"paper,":[35],"(1)":[36],"we":[37],"report":[38],"increase":[41],"by":[42,80],"not":[45],"significant":[47],"(only":[48],"+4.25%":[49],"compared":[50],"5":[52],"track":[53],"FinFET":[54],"INV),":[55],"and":[56,86],"(2)":[57],"propose":[58],"design":[60],"methodology":[61,75],"optimizes":[63],"parasitics":[65,79],"of":[66,95],"CFET":[67,96],"standard":[68],"cells":[69],"make":[71],"happen.":[73],"Our":[74],"shows":[76],"improvements":[77],"in":[78],"up":[81],"8.15%":[83],"for":[84,88],"capacitance":[85],"32.73%":[87],"resistance":[89],"when":[90],"comparing":[91],"two":[93],"types":[94],"structures.":[97]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}