{"id":"https://openalex.org/W3217323523","doi":"https://doi.org/10.1109/isocc53507.2021.9613905","title":"Trend of Emerging Non-Volatile Memory for AI Processor","display_name":"Trend of Emerging Non-Volatile Memory for AI Processor","publication_year":2021,"publication_date":"2021-10-06","ids":{"openalex":"https://openalex.org/W3217323523","doi":"https://doi.org/10.1109/isocc53507.2021.9613905","mag":"3217323523"},"language":"en","primary_location":{"id":"doi:10.1109/isocc53507.2021.9613905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc53507.2021.9613905","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 18th International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038647640","display_name":"Liang Chang","orcid":"https://orcid.org/0000-0002-6685-5576"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Liang Chang","raw_affiliation_strings":["University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100398935","display_name":"Chenglong Li","orcid":"https://orcid.org/0000-0003-0111-0749"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenglong Li","raw_affiliation_strings":["University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036019546","display_name":"Xin Zhao","orcid":"https://orcid.org/0009-0009-0149-6072"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin Zhao","raw_affiliation_strings":["University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101705740","display_name":"Zixuan Zhu","orcid":"https://orcid.org/0009-0000-2925-7975"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zixuan Zhu","raw_affiliation_strings":["University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086160027","display_name":"Tong Yi","orcid":"https://orcid.org/0000-0002-6774-9732"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yi Tong","raw_affiliation_strings":["Gusu Laboratory of Materials, Suzhou, China"],"affiliations":[{"raw_affiliation_string":"Gusu Laboratory of Materials, Suzhou, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103251262","display_name":"Shuisheng Lin","orcid":"https://orcid.org/0000-0003-2296-8146"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shuisheng Lin","raw_affiliation_strings":["University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5119011974","display_name":"Jun Zhou","orcid":"https://orcid.org/0000-0001-5394-9787"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Zhou","raw_affiliation_strings":["University of Electronic Science and Technology of China, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5038647640"],"corresponding_institution_ids":["https://openalex.org/I150229711"],"apc_list":null,"apc_paid":null,"fwci":0.3008,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.57553421,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"223","last_page":"224"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.8674004077911377},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.844430685043335},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7494412660598755},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6818020343780518},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.6024307608604431},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5517796277999878},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.4722941219806671},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4609447419643402},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.45092225074768066},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4319981038570404},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4286278486251831},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42687657475471497},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.42611682415008545},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4145599603652954},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40706175565719604},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.40485161542892456},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.3646557927131653},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.36090952157974243},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24380257725715637},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16373619437217712},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14819741249084473},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07456231117248535}],"concepts":[{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.8674004077911377},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.844430685043335},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7494412660598755},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6818020343780518},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.6024307608604431},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5517796277999878},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.4722941219806671},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4609447419643402},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.45092225074768066},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4319981038570404},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4286278486251831},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42687657475471497},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.42611682415008545},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4145599603652954},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40706175565719604},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.40485161542892456},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.3646557927131653},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.36090952157974243},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24380257725715637},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16373619437217712},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14819741249084473},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07456231117248535}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc53507.2021.9613905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc53507.2021.9613905","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 18th International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2594135538","https://openalex.org/W2789899229","https://openalex.org/W2793776854","https://openalex.org/W2794194363","https://openalex.org/W2921351161","https://openalex.org/W2922523256","https://openalex.org/W3015980402","https://openalex.org/W3016147292","https://openalex.org/W3048446883","https://openalex.org/W3093701126","https://openalex.org/W3134195144","https://openalex.org/W3135060602","https://openalex.org/W3166510811"],"related_works":["https://openalex.org/W1494152240","https://openalex.org/W1030357071","https://openalex.org/W2171888576","https://openalex.org/W2079019992","https://openalex.org/W63036740","https://openalex.org/W2188534734","https://openalex.org/W2136485767","https://openalex.org/W1981423095","https://openalex.org/W1572401189","https://openalex.org/W4238754064"],"abstract_inverted_index":{"Processing":[0],"unit":[1,73],"and":[2,19,57,74,90,98,102,115],"memory":[3,23,48],"are":[4,13],"key":[5],"components":[6],"for":[7],"artificial":[8],"intelligent":[9],"(AI)":[10],"processor,":[11],"which":[12,61],"developed":[14],"by":[15],"the":[16,33,45,84,94,108],"CMOS":[17],"technology":[18,27],"static":[20],"random":[21],"access":[22],"(SRAM),":[24],"respectively.":[25],"As":[26],"scaling":[28],"down":[29],"to":[30,41,65,69],"sub-30":[31],"nm,":[32],"leakage":[34],"current":[35],"has":[36],"become":[37],"a":[38,81,119],"critical":[39],"issue":[40],"AI":[42,67,120],"processor.":[43],"Recently,":[44],"emerging":[46],"non-volatile":[47],"is":[49],"mature":[50],"gradually,":[51],"such":[52],"as":[53,100],"Magnetic":[54],"RAM":[55,59],"(MRAM)":[56],"Resistive":[58],"(RRAM),":[60],"can":[62,117],"be":[63,118],"used":[64],"develop":[66],"processor":[68],"alternate":[70],"both":[71,113],"processing":[72],"memory.":[75],"In":[76],"this":[77],"work,":[78],"we":[79,111],"provide":[80],"survey":[82],"on":[83,88,107],"recent":[85,109],"tape-out":[86],"work":[87],"MRAM":[89,97,114],"RRAM.":[91],"We":[92],"discuss":[93],"trend":[95],"of":[96],"RRAM":[99,116],"buffer/Cache,":[101],"computingin":[103],"Memory":[104],"architecture.":[105],"Based":[106],"developments,":[110],"predict":[112],"product":[121],"soon.":[122]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}