{"id":"https://openalex.org/W3022827830","doi":"https://doi.org/10.1109/isocc47750.2019.9078524","title":"Transition-delay Test Methodology for Designs with Self-gating","display_name":"Transition-delay Test Methodology for Designs with Self-gating","publication_year":2019,"publication_date":"2019-10-06","ids":{"openalex":"https://openalex.org/W3022827830","doi":"https://doi.org/10.1109/isocc47750.2019.9078524","mag":"3022827830"},"language":"en","primary_location":{"id":"doi:10.1109/isocc47750.2019.9078524","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc47750.2019.9078524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100384996","display_name":"Jihye Kim","orcid":"https://orcid.org/0000-0002-5719-8180"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jihye Kim","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100712406","display_name":"Sangjun Lee","orcid":"https://orcid.org/0000-0002-8687-8329"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sangjun Lee","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029381475","display_name":"Minho Moon","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Minho Moon","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068528309","display_name":"Sungho Kang","orcid":"https://orcid.org/0000-0002-7093-2095"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungho Kang","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"93","last_page":"94"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.7284086346626282},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6226390600204468},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5964834094047546},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5834006071090698},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5747770667076111},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5304590463638306},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4860954284667969},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4776517152786255},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.445472776889801},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4453304708003998},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.44396060705184937},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42645618319511414},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42601072788238525},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.42452430725097656},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3920144736766815},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2576080560684204},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22976922988891602},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.18194395303726196},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.17047923803329468},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15821942687034607},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1374213993549347},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11899006366729736},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.11201074719429016},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11099469661712646}],"concepts":[{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.7284086346626282},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6226390600204468},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5964834094047546},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5834006071090698},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5747770667076111},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5304590463638306},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4860954284667969},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4776517152786255},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.445472776889801},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4453304708003998},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.44396060705184937},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42645618319511414},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42601072788238525},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.42452430725097656},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3920144736766815},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2576080560684204},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22976922988891602},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.18194395303726196},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.17047923803329468},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15821942687034607},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1374213993549347},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11899006366729736},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.11201074719429016},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11099469661712646},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc47750.2019.9078524","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc47750.2019.9078524","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2035342163","https://openalex.org/W2411662954","https://openalex.org/W2596017129","https://openalex.org/W2608484494","https://openalex.org/W2948345470"],"related_works":["https://openalex.org/W2152979262","https://openalex.org/W3127845477","https://openalex.org/W2485892467","https://openalex.org/W4252084893","https://openalex.org/W1949070338","https://openalex.org/W2938543345","https://openalex.org/W1510566755","https://openalex.org/W4390197045","https://openalex.org/W2102121056","https://openalex.org/W2003272148"],"abstract_inverted_index":{"Power":[0],"reduction":[1,19],"is":[2,15,24,46,53,91],"one":[3,25],"of":[4,26,30,68],"the":[5,27,42,49,62,79,95,107,110],"most":[6],"important":[7],"design":[8],"factors":[9,29],"for":[10,17,56],"system-on-chip.":[11],"The":[12,101],"self-gating":[13,43,98],"method":[14],"used":[16],"power":[18,32],"in":[20,78],"clock":[21],"networks,":[22],"which":[23,93],"main":[28],"dynamic":[31],"consumption.":[33],"However,":[34],"scan":[35],"test":[36,50,70,89],"patterns":[37,71],"can":[38],"be":[39],"increased":[40,73],"by":[41],"insertion.":[44],"It":[45],"observed":[47],"that":[48,65,105],"pattern":[51,113],"increase":[52,114],"very":[54],"severe":[55],"transition":[57],"delay":[58],"(TD)":[59],"faults":[60],"with":[61,74],"experimental":[63,102],"results":[64,103],"over":[66],"250%":[67],"TD":[69,88,112],"are":[72],"XOR":[75],"selfgating":[76],"insertion":[77],"industrial":[80],"circuits.":[81],"In":[82],"this":[83],"paper,":[84],"a":[85],"new":[86,108],"efficient":[87],"methodology":[90],"proposed":[92],"uses":[94],"data":[96],"selectable":[97],"(DSSG)":[99],"structure.":[100],"show":[104],"using":[106],"methodology,":[109],"average":[111],"ratio":[115],"has":[116],"dropped":[117],"to":[118],"under":[119],"50%.":[120]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}