{"id":"https://openalex.org/W3011522205","doi":"https://doi.org/10.1109/isocc47750.2019.9027674","title":"Frequency Discriminator Using a Simple AD Converter for Interface Systems","display_name":"Frequency Discriminator Using a Simple AD Converter for Interface Systems","publication_year":2019,"publication_date":"2019-10-06","ids":{"openalex":"https://openalex.org/W3011522205","doi":"https://doi.org/10.1109/isocc47750.2019.9027674","mag":"3011522205"},"language":"en","primary_location":{"id":"doi:10.1109/isocc47750.2019.9027674","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc47750.2019.9027674","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015591823","display_name":"Sanshiro Kimura","orcid":null},"institutions":[{"id":"https://openalex.org/I139159150","display_name":"University of Shiga Prefecture","ror":"https://ror.org/02dvjfw95","country_code":"JP","type":"education","lineage":["https://openalex.org/I139159150"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Sanshiro Kimura","raw_affiliation_strings":["The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan","institution_ids":["https://openalex.org/I139159150"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042945944","display_name":"Atsuto Imajo","orcid":null},"institutions":[{"id":"https://openalex.org/I139159150","display_name":"University of Shiga Prefecture","ror":"https://ror.org/02dvjfw95","country_code":"JP","type":"education","lineage":["https://openalex.org/I139159150"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsuto Imajo","raw_affiliation_strings":["The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan","institution_ids":["https://openalex.org/I139159150"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082242690","display_name":"Toshiyuki Inoue","orcid":"https://orcid.org/0000-0002-6621-1412"},"institutions":[{"id":"https://openalex.org/I139159150","display_name":"University of Shiga Prefecture","ror":"https://ror.org/02dvjfw95","country_code":"JP","type":"education","lineage":["https://openalex.org/I139159150"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshiyuki Inoue","raw_affiliation_strings":["The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan","institution_ids":["https://openalex.org/I139159150"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038761727","display_name":"Akira Tsuchiya","orcid":"https://orcid.org/0000-0002-3299-9328"},"institutions":[{"id":"https://openalex.org/I139159150","display_name":"University of Shiga Prefecture","ror":"https://ror.org/02dvjfw95","country_code":"JP","type":"education","lineage":["https://openalex.org/I139159150"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akira Tsuchiya","raw_affiliation_strings":["The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan","institution_ids":["https://openalex.org/I139159150"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022381888","display_name":"Keiji Kishine","orcid":"https://orcid.org/0000-0003-3213-6650"},"institutions":[{"id":"https://openalex.org/I139159150","display_name":"University of Shiga Prefecture","ror":"https://ror.org/02dvjfw95","country_code":"JP","type":"education","lineage":["https://openalex.org/I139159150"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Keiji Kishine","raw_affiliation_strings":["The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Shiga Prefecture, 2500, Hassaka, Hikone, Shiga, Japan","institution_ids":["https://openalex.org/I139159150"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I139159150"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.32347359,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"128","last_page":"129"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/discriminator","display_name":"Discriminator","score":0.9571080207824707},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.7855030298233032},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.7308530211448669},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6829973459243774},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5968299508094788},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.5541431903839111},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5284578204154968},{"id":"https://openalex.org/keywords/parallel-port","display_name":"Parallel port","score":0.46986302733421326},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4377218782901764},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4135615825653076},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3234558701515198},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28116750717163086},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2059060037136078},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14630913734436035},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.10951954126358032}],"concepts":[{"id":"https://openalex.org/C2779803651","wikidata":"https://www.wikidata.org/wiki/Q5282088","display_name":"Discriminator","level":3,"score":0.9571080207824707},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.7855030298233032},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.7308530211448669},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6829973459243774},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5968299508094788},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.5541431903839111},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5284578204154968},{"id":"https://openalex.org/C202683721","wikidata":"https://www.wikidata.org/wiki/Q190440","display_name":"Parallel port","level":3,"score":0.46986302733421326},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4377218782901764},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4135615825653076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3234558701515198},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28116750717163086},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2059060037136078},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14630913734436035},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.10951954126358032},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc47750.2019.9027674","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc47750.2019.9027674","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/10","score":0.6899999976158142,"display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1721554232","https://openalex.org/W2117885266","https://openalex.org/W6637710601"],"related_works":["https://openalex.org/W4293202849","https://openalex.org/W1980965563","https://openalex.org/W1489300767","https://openalex.org/W2387995142","https://openalex.org/W4380714744","https://openalex.org/W4319453655","https://openalex.org/W2089959425","https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W3011522205"],"abstract_inverted_index":{"In":[0,23],"optical":[1],"communication":[2],"systems,":[3],"simple":[4,38,52],"and":[5,102],"compact":[6],"interface":[7,39],"to":[8,20],"control":[9],"circuits":[10],"appropriately":[11],"from":[12],"outside":[13],"chips":[14],"or":[15],"modules":[16],"is":[17],"strongly":[18],"expected":[19],"be":[21],"provided.":[22],"our":[24],"previous":[25],"work,":[26],"Single-Channel":[27],"Multi-Port":[28],"Control":[29],"system":[30],"(SCMPC)":[31],"was":[32,92,106],"shown":[33],"as":[34],"one":[35],"of":[36,84],"the":[37,58,85,89,103],"systems.":[40],"To":[41],"make":[42],"SCMPC":[43],"compact,":[44],"we":[45],"propose":[46],"a":[47,51,74,99],"frequency":[48,104],"discriminator":[49],"using":[50],"AD":[53],"converter":[54],"for":[55,98],"receiver":[56,62],"in":[57,77],"system.":[59],"The":[60,82],"proposed":[61],"can":[63],"handle":[64],"high":[65],"speed":[66,91],"operation.":[67],"We":[68],"confirm":[69],"its":[70],"benefits":[71],"by":[72,108],"performing":[73],"post-layout":[75],"simulation":[76,86],"an":[78],"180-nm":[79],"CMOS":[80],"process.":[81],"results":[83],"show":[87],"that":[88,97],"discrimination":[90],"two":[93],"times":[94],"faster":[95],"than":[96],"conventional":[100],"circuit":[101],"resolution":[105],"improved":[107],"about":[109],"67%.":[110]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
