{"id":"https://openalex.org/W2915217901","doi":"https://doi.org/10.1109/isocc.2018.8649940","title":"The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization","display_name":"The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization","publication_year":2018,"publication_date":"2018-11-01","ids":{"openalex":"https://openalex.org/W2915217901","doi":"https://doi.org/10.1109/isocc.2018.8649940","mag":"2915217901"},"language":"en","primary_location":{"id":"doi:10.1109/isocc.2018.8649940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2018.8649940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089374633","display_name":"Yujie Huang","orcid":"https://orcid.org/0000-0001-7934-7872"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yujie Huang","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103027800","display_name":"Yujie Cai","orcid":"https://orcid.org/0000-0003-2166-0748"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yujie Cai","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073266325","display_name":"Minge Jing","orcid":"https://orcid.org/0009-0005-0446-5600"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Minge Jing","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066674438","display_name":"Jun Han","orcid":"https://orcid.org/0000-0002-5245-0754"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Han","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085004179","display_name":"Yibo Fan","orcid":"https://orcid.org/0000-0003-2523-8261"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yibo Fan","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100656792","display_name":"Xiaoyang Zeng","orcid":"https://orcid.org/0000-0003-3986-137X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyang Zeng","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.19290051,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"123","last_page":"124"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7891669273376465},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.6718188524246216},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5497565269470215},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5144253373146057},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5109833478927612},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.49935102462768555},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.48414379358291626},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4657244384288788},{"id":"https://openalex.org/keywords/recursion","display_name":"Recursion (computer science)","score":0.46525460481643677},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.4580267071723938},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.45103204250335693},{"id":"https://openalex.org/keywords/soft-decision-decoder","display_name":"Soft-decision decoder","score":0.4350181221961975},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.41580644249916077},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3743354082107544},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3655232787132263}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7891669273376465},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.6718188524246216},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5497565269470215},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5144253373146057},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5109833478927612},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.49935102462768555},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.48414379358291626},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4657244384288788},{"id":"https://openalex.org/C168773036","wikidata":"https://www.wikidata.org/wiki/Q264164","display_name":"Recursion (computer science)","level":2,"score":0.46525460481643677},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.4580267071723938},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.45103204250335693},{"id":"https://openalex.org/C185588885","wikidata":"https://www.wikidata.org/wiki/Q7553811","display_name":"Soft-decision decoder","level":3,"score":0.4350181221961975},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.41580644249916077},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3743354082107544},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3655232787132263},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc.2018.8649940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2018.8649940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1993492094","https://openalex.org/W2018055497","https://openalex.org/W2023451687","https://openalex.org/W2143766527","https://openalex.org/W2166029537"],"related_works":["https://openalex.org/W1976679120","https://openalex.org/W4281614748","https://openalex.org/W2798215405","https://openalex.org/W2990962948","https://openalex.org/W2377519369","https://openalex.org/W2765883196","https://openalex.org/W1998195961","https://openalex.org/W3094476157","https://openalex.org/W2385597935","https://openalex.org/W2146716617"],"abstract_inverted_index":{"With":[0],"the":[1,31,60,71,81,84,90,109,126],"extensive":[2],"use":[3],"of":[4,13,59,74,112],"hardware":[5,11,23,122,156],"acceleration":[6],"for":[7,36,133],"complex":[8],"algorithms,":[9],"fast":[10],"implementations":[12],"those":[14],"algorithms":[15],"with":[16,25,55],"HLS":[17,26,56,145],"become":[18],"necessary.":[19],"However,":[20],"high":[21,149],"performance":[22,150],"generated":[24],"needs":[27],"numerous":[28],"skills":[29],"and":[30,107,114,124,140],"successive-cancellation":[32],"(SC)":[33],"decoding":[34,76,86],"algorithm":[35,87],"polar":[37],"code,":[38],"which":[39,101,135,153],"is":[40],"widely":[41],"used":[42],"in":[43,62,83,132,144],"5G":[44],"era,":[45],"can't":[46],"be":[47],"converted":[48],"from":[49],"c":[50],"code":[51,54],"to":[52,89,98,120,146],"verilog":[53],"directly":[57],"because":[58],"recursion":[61,82],"it.":[63],"In":[64],"this":[65],"paper,":[66],"we":[67,79,93,129],"firstly":[68],"find":[69],"out":[70],"operation":[72,116],"laws":[73],"SC":[75,85,151],"algorithm;":[77],"secondly,":[78],"expand":[80],"according":[88],"laws;":[91],"thirdly,":[92],"convert":[94],"float":[95],"point":[96,100],"data":[97],"fixed":[99],"reduces":[102,136],"LUT":[103],"resources":[104],"by":[105,138],"63.5%":[106],"simplify":[108],"function":[110],"consisting":[111],"exponential":[113],"logarithm":[115],"through":[117],"Taylor":[118],"Expansion":[119],"reduce":[121],"resource":[123],"accelerate":[125],"hardware;":[127],"finally,":[128],"apply":[130],"pipeline":[131],"loop":[134],"cycles":[137],"29%":[139],"call":[141],"on-chip":[142],"RAM":[143],"quickly":[147],"generate":[148],"decoder":[152],"consumes":[154],"low":[155],"resources.":[157]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
