{"id":"https://openalex.org/W2805712071","doi":"https://doi.org/10.1109/isocc.2017.8368867","title":"Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS","display_name":"Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS","publication_year":2017,"publication_date":"2017-11-01","ids":{"openalex":"https://openalex.org/W2805712071","doi":"https://doi.org/10.1109/isocc.2017.8368867","mag":"2805712071"},"language":"en","primary_location":{"id":"doi:10.1109/isocc.2017.8368867","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2017.8368867","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100777162","display_name":"Yongho Lee","orcid":"https://orcid.org/0000-0002-9181-4186"},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Yongho Lee","raw_affiliation_strings":["High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul, Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101402883","display_name":"Seungsoo Kim","orcid":"https://orcid.org/0000-0001-8154-7515"},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seungsoo Kim","raw_affiliation_strings":["High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul, Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025117341","display_name":"Hyunchol Shin","orcid":"https://orcid.org/0000-0003-1141-3428"},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyunchol Shin","raw_affiliation_strings":["High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul, Korea","institution_ids":["https://openalex.org/I161024014"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100777162"],"corresponding_institution_ids":["https://openalex.org/I161024014"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21343837,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"230","last_page":"231"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12801","display_name":"Bluetooth and Wireless Communication Technologies","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.866282045841217},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.8460884094238281},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.7433274388313293},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.7389976978302002},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7046871185302734},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.6871602535247803},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.6498338580131531},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.5178663730621338},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5139448046684265},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4678047001361847},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4502144455909729},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3520786464214325},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3258114755153656},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.2650509178638458}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.866282045841217},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.8460884094238281},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.7433274388313293},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.7389976978302002},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7046871185302734},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.6871602535247803},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.6498338580131531},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.5178663730621338},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5139448046684265},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4678047001361847},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4502144455909729},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3520786464214325},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3258114755153656},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.2650509178638458},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc.2017.8368867","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2017.8368867","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2601852209"],"related_works":["https://openalex.org/W2371029054","https://openalex.org/W3145870900","https://openalex.org/W2394106628","https://openalex.org/W2350996794","https://openalex.org/W2371350995","https://openalex.org/W2088877925","https://openalex.org/W2384857702","https://openalex.org/W2393391611","https://openalex.org/W2367423162","https://openalex.org/W2370071821"],"abstract_inverted_index":{"A":[0],"fractional-N":[1],"PLL":[2,20,33],"synthesizer":[3,21,81,86],"is":[4,22,35,82],"designed":[5,23],"in":[6,24],"65":[7],"nm":[8],"CMOS":[9],"general":[10],"process":[11,73],"for":[12,43],"Bluetooth":[13],"low-energy":[14],"applications.":[15],"For":[16],"low-power":[17],"consumption,":[18],"the":[19,40,75,80],"a":[25,68],"single":[26],"1-V":[27],"supply.":[28],"The":[29,47,85],"tuning":[30],"range":[31],"of":[32,79],"Synthesizer":[34],"1.9-2.7":[36],"GHz":[37],"to":[38],"cover":[39],"ISM":[41],"band":[42],"1/5-fRF":[44],"sliding-IF":[45],"receiver.":[46],"simulated":[48],"VCO":[49,70],"phase":[50],"noises":[51],"at":[52,61],"1":[53,91],"MHz":[54],"offset":[55],"are":[56],"-110":[57],"and":[58,63],"-120":[59],"dBc/Hz":[60],"2.7":[62],"1.9":[64],"GHz,":[65],"respectively.":[66],"With":[67],"fast":[69],"frequency":[71],"calibration":[72],"included,":[74],"total":[76],"lock":[77],"time":[78],"12":[83],"\u03bcs.":[84],"dissipates":[87],"3":[88],"mW":[89],"from":[90],"V":[92],"supply":[93],"voltage.":[94]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}