{"id":"https://openalex.org/W2549835187","doi":"https://doi.org/10.1109/isocc.2012.6407115","title":"An efficient dual-supply design for low-power mobile systems","display_name":"An efficient dual-supply design for low-power mobile systems","publication_year":2012,"publication_date":"2012-11-01","ids":{"openalex":"https://openalex.org/W2549835187","doi":"https://doi.org/10.1109/isocc.2012.6407115","mag":"2549835187"},"language":"en","primary_location":{"id":"doi:10.1109/isocc.2012.6407115","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2012.6407115","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090750669","display_name":"Hoi-Jin Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hoi-Jin Lee","raw_affiliation_strings":["SOC Processor Development Team, System LSI, Samsung Electronics, Giheung, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SOC Processor Development Team, System LSI, Samsung Electronics, Giheung, Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069448134","display_name":"Youngmin Shin","orcid":"https://orcid.org/0000-0003-3457-2720"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngmin Shin","raw_affiliation_strings":["SOC Processor Development Team, System LSI, Samsung Electronics, Giheung, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SOC Processor Development Team, System LSI, Samsung Electronics, Giheung, Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108544072","display_name":"Jae Cheol Son","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jae Cheol Son","raw_affiliation_strings":["SOC Processor Development Team, System LSI, Samsung Electronics, Giheung, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SOC Processor Development Team, System LSI, Samsung Electronics, Giheung, Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084741187","display_name":"Tae Hee Han","orcid":"https://orcid.org/0000-0001-8508-7536"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Tae Hee Han","raw_affiliation_strings":["College of Information & Communication Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information & Communication Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012892234","display_name":"Bai\u2010Sun Kong","orcid":"https://orcid.org/0000-0002-1077-7038"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Bai-Sun Kong","raw_affiliation_strings":["College of Information & Communication Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information & Communication Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.32274355,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"359","last_page":"362"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7832280993461609},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5901592969894409},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5792681574821472},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5537267923355103},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.5251376628875732},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4603573679924011},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4469435214996338},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.31260091066360474},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2910316586494446},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26902225613594055},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19928869605064392},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17199328541755676},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.12622126936912537}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7832280993461609},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5901592969894409},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5792681574821472},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5537267923355103},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.5251376628875732},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4603573679924011},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4469435214996338},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.31260091066360474},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2910316586494446},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26902225613594055},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19928869605064392},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17199328541755676},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.12622126936912537},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc.2012.6407115","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2012.6407115","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8600000143051147}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1489295529","https://openalex.org/W1658200930","https://openalex.org/W1982305968","https://openalex.org/W1997742530","https://openalex.org/W2096889604","https://openalex.org/W2099250769","https://openalex.org/W2121169595","https://openalex.org/W2121190917","https://openalex.org/W2137229108","https://openalex.org/W2158881717","https://openalex.org/W2160130898","https://openalex.org/W2161521898","https://openalex.org/W2169278276","https://openalex.org/W2554690018","https://openalex.org/W6674376720"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W4386968318","https://openalex.org/W2137310043","https://openalex.org/W2337711143","https://openalex.org/W2031867410","https://openalex.org/W2205497670","https://openalex.org/W1513897901","https://openalex.org/W1994439638","https://openalex.org/W2565835957","https://openalex.org/W1644931186"],"abstract_inverted_index":{"This":[0],"paper":[1],"overviews":[2],"dual-supply":[3,14,33,52],"design":[4,15,22,34],"for":[5,19],"low-power":[6],"mobile":[7],"systems":[8],"in":[9,23,66,123],"deep":[10],"sub-micron":[11],"technology.":[12],"Various":[13],"schemes":[16],"were":[17],"investigated":[18],"real":[20],"world":[21],"terms":[24,67],"of":[25,63,68],"power":[26,100,125],"efficiency.":[27],"The":[28],"analysis":[29],"showed":[30],"that":[31,44],"a":[32,37,113],"applied":[35,45],"to":[36,46,81,115],"clock":[38,53,104],"network":[39,54],"was":[40],"more":[41,99,124],"efficient":[42],"than":[43],"data-path":[47],"logics.":[48],"For":[49],"example,":[50],"the":[51,61,82,103,107],"with":[55],"clock-gating":[56,108],"level":[57,64,95,109],"converter":[58,110],"can":[59,74,97,111],"minimize":[60],"penalties":[62],"conversion":[65],"power,":[69],"area,":[70],"and":[71],"performance.":[72],"It":[73],"also":[75],"achieve":[76],"higher":[77],"operating":[78],"frequency":[79],"due":[80],"mitigated":[83],"timing":[84],"constraint":[85],"on":[86],"gated":[87],"clocks.":[88],"Frequency":[89],"doubling":[90],"readily":[91],"derived":[92],"from":[93],"existing":[94],"converters":[96],"save":[98],"by":[101],"halving":[102],"frequency.":[105],"Furthermore,":[106],"enable":[112],"system":[114],"exploit":[116],"pulse-based":[117],"flip-flops":[118],"without":[119],"pulse":[120],"generators,":[121],"resulting":[122],"reduction.":[126]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
