{"id":"https://openalex.org/W2550909083","doi":"https://doi.org/10.1109/isocc.2012.6407049","title":"Spur suppression in frequency synthesizer using switched capacitor array","display_name":"Spur suppression in frequency synthesizer using switched capacitor array","publication_year":2012,"publication_date":"2012-11-01","ids":{"openalex":"https://openalex.org/W2550909083","doi":"https://doi.org/10.1109/isocc.2012.6407049","mag":"2550909083"},"language":"en","primary_location":{"id":"doi:10.1109/isocc.2012.6407049","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2012.6407049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101765300","display_name":"Debashis Mandal","orcid":"https://orcid.org/0000-0003-0644-1141"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Debashis Mandal","raw_affiliation_strings":["Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109378297","display_name":"Pradip Mandal","orcid":"https://orcid.org/0000-0002-3767-7299"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pradip Mandal","raw_affiliation_strings":["Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022460657","display_name":"Tarun Kanti Bhattacharyya","orcid":"https://orcid.org/0000-0002-7699-6436"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tarun Kanti Bhattacharyya","raw_affiliation_strings":["Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101765300"],"corresponding_institution_ids":["https://openalex.org/I145894827"],"apc_list":null,"apc_paid":null,"fwci":2.7005,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.91079611,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"100","last_page":"103"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.762454628944397},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.7043452262878418},{"id":"https://openalex.org/keywords/switched-capacitor","display_name":"Switched capacitor","score":0.7005085945129395},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.6956775188446045},{"id":"https://openalex.org/keywords/spur","display_name":"Spur","score":0.6767820119857788},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6473197937011719},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6007466316223145},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.5919761657714844},{"id":"https://openalex.org/keywords/frequency-offset","display_name":"Frequency offset","score":0.5081593990325928},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4556170105934143},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42851245403289795},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4256893992424011},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3579871654510498},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24894142150878906},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.12585672736167908},{"id":"https://openalex.org/keywords/orthogonal-frequency-division-multiplexing","display_name":"Orthogonal frequency-division multiplexing","score":0.07325953245162964}],"concepts":[{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.762454628944397},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.7043452262878418},{"id":"https://openalex.org/C103357873","wikidata":"https://www.wikidata.org/wiki/Q572656","display_name":"Switched capacitor","level":4,"score":0.7005085945129395},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.6956775188446045},{"id":"https://openalex.org/C2779821383","wikidata":"https://www.wikidata.org/wiki/Q7581537","display_name":"Spur","level":2,"score":0.6767820119857788},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6473197937011719},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6007466316223145},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.5919761657714844},{"id":"https://openalex.org/C49319798","wikidata":"https://www.wikidata.org/wiki/Q5502874","display_name":"Frequency offset","level":4,"score":0.5081593990325928},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4556170105934143},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42851245403289795},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4256893992424011},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3579871654510498},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24894142150878906},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.12585672736167908},{"id":"https://openalex.org/C40409654","wikidata":"https://www.wikidata.org/wiki/Q375889","display_name":"Orthogonal frequency-division multiplexing","level":3,"score":0.07325953245162964},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc.2012.6407049","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2012.6407049","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International SoC Design Conference (ISOCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1966204301","https://openalex.org/W1972557390","https://openalex.org/W2001078510","https://openalex.org/W2002948873","https://openalex.org/W2045294741","https://openalex.org/W2064715136","https://openalex.org/W2107514446","https://openalex.org/W2118269375","https://openalex.org/W2126749795","https://openalex.org/W2149785845","https://openalex.org/W2152316587","https://openalex.org/W2154473183","https://openalex.org/W2165238044","https://openalex.org/W6641800613","https://openalex.org/W6682739945"],"related_works":["https://openalex.org/W4289538008","https://openalex.org/W3186427148","https://openalex.org/W2138282914","https://openalex.org/W2065850627","https://openalex.org/W2017012638","https://openalex.org/W2071885361","https://openalex.org/W1966793535","https://openalex.org/W2064715136","https://openalex.org/W2356983383","https://openalex.org/W3008457164"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"a":[5,21,26,101],"PLL":[6,37],"based":[7],"frequency":[8,64,76],"synthesizer":[9,65],"architecture":[10],"having":[11],"low":[12],"spur.":[13],"Using":[14],"an":[15,62],"array":[16,52],"of":[17,59,70,104],"switched":[18],"capacitors":[19],"and":[20,77,108],"delay":[22],"locked":[23],"loop":[24],"(DLL),":[25],"periodic":[27],"charge":[28],"distribution":[29],"technique":[30],"to":[31,100],"suppress":[32],"reference":[33,81],"spur":[34,96,121],"in":[35,86],"the":[36,44,50,54,57,60,120],"has":[38,83],"been":[39,84],"adopted.":[40],"The":[41],"DLL":[42],"provides":[43],"equispaced":[45],"M":[46],"instances":[47],"at":[48,112,122],"which":[49],"capacitor":[51],"distributes":[53],"charge.":[55],"For":[56],"validation":[58],"concept,":[61],"integer-N":[63],"with":[66,98],"four":[67],"times":[68],"repetition":[69],"ripples":[71],"for":[72],"916":[73],"MHz":[74,79,116,124],"output":[75,95],"2":[78],"input":[80],"frequency,":[82],"designed":[85],"180":[87],"nm":[88],"CMOS":[89],"technology.":[90],"Cadence":[91],"Spectre":[92],"simulation":[93],"shows":[94],"improvement,":[97],"respect":[99],"conventional":[102],"architecture,":[103],"about":[105],"59,":[106],"75":[107],"65":[109],"dB":[110],"respectively":[111],"2,":[113],"4,":[114],"6":[115],"offset":[117,125],"frequencies":[118],"while":[119],"8":[123],"remains":[126],"unchanged.":[127]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2012,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}