{"id":"https://openalex.org/W2554699452","doi":"https://doi.org/10.1109/isocc.2011.6138669","title":"Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy","display_name":"Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W2554699452","doi":"https://doi.org/10.1109/isocc.2011.6138669","mag":"2554699452"},"language":"en","primary_location":{"id":"doi:10.1109/isocc.2011.6138669","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2011.6138669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International SoC Design Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082434121","display_name":"Teruki Nakasato","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Teruki Nakasato","raw_affiliation_strings":["Department of Electronic and Information System, University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic and Information System, University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071803491","display_name":"Toru Nakura","orcid":"https://orcid.org/0000-0001-5945-3918"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toru Nakura","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Bunkyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"150","last_page":"153"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6674754023551941},{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.6570187211036682},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6478140950202942},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5468111634254456},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5361694097518921},{"id":"https://openalex.org/keywords/stress","display_name":"Stress (linguistics)","score":0.47211945056915283},{"id":"https://openalex.org/keywords/mean-time-between-failures","display_name":"Mean time between failures","score":0.467110276222229},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.43595123291015625},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4280228018760681},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.4195680618286133},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41031962633132935},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3779488801956177},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3197099566459656},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2996380925178528},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28545424342155457},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.2732807397842407},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23722338676452637},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.13073527812957764},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11634910106658936},{"id":"https://openalex.org/keywords/failure-rate","display_name":"Failure rate","score":0.0828736424446106},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07297161221504211},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.06313508749008179}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6674754023551941},{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.6570187211036682},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6478140950202942},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5468111634254456},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5361694097518921},{"id":"https://openalex.org/C21036866","wikidata":"https://www.wikidata.org/wiki/Q181767","display_name":"Stress (linguistics)","level":2,"score":0.47211945056915283},{"id":"https://openalex.org/C44154001","wikidata":"https://www.wikidata.org/wiki/Q754940","display_name":"Mean time between failures","level":3,"score":0.467110276222229},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.43595123291015625},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4280228018760681},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.4195680618286133},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41031962633132935},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3779488801956177},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3197099566459656},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2996380925178528},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28545424342155457},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.2732807397842407},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23722338676452637},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.13073527812957764},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11634910106658936},{"id":"https://openalex.org/C163164238","wikidata":"https://www.wikidata.org/wiki/Q2737027","display_name":"Failure rate","level":2,"score":0.0828736424446106},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07297161221504211},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.06313508749008179},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isocc.2011.6138669","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isocc.2011.6138669","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International SoC Design Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1991891926","https://openalex.org/W2009919741","https://openalex.org/W2010015693","https://openalex.org/W2012039880","https://openalex.org/W2056796532","https://openalex.org/W2129314919","https://openalex.org/W2134869654","https://openalex.org/W2161032316","https://openalex.org/W2532588824","https://openalex.org/W2542080808","https://openalex.org/W6652741520"],"related_works":["https://openalex.org/W1983353130","https://openalex.org/W4400370279","https://openalex.org/W168429299","https://openalex.org/W1513192318","https://openalex.org/W2064185557","https://openalex.org/W2118309485","https://openalex.org/W2044425520","https://openalex.org/W2184065029","https://openalex.org/W2486596002","https://openalex.org/W1602382472"],"abstract_inverted_index":{"Moore's":[0],"law":[1],"keeps":[2],"shrinking":[3],"the":[4,11,25,31,55,65,71,109,112],"transistor":[5,79],"size,":[6],"and":[7,29,46,106],"timing":[8,36],"degradation":[9,28],"of":[10,24,54,64,111],"small":[12],"transistors":[13],"are":[14],"becoming":[15],"critical.":[16],"Negative":[17],"Bias":[18],"Temperature":[19],"Instability":[20],"(NBTI)":[21],"is":[22],"one":[23,53,63],"dominant":[26],"cause":[27],"increasing":[30],"path":[32,66,73],"delay,":[33],"resulting":[34],"in":[35],"errors.":[37],"This":[38],"paper":[39],"introduces":[40],"altered":[41],"Fine-Grain":[42],"Redundant":[43],"(FGR)":[44],"logic":[45,51,58],"Stress-balance":[47],"Flip-Flops":[48],"(SBFFs).":[49],"FGR":[50,105],"uses":[52],"two":[56],"identical":[57],"paths":[59],"alternately":[60],"so":[61,83],"that":[62],"recovers":[67],"NBTI":[68],"stress":[69],"while":[70],"other":[72],"works.":[74],"The":[75,90],"SBFF":[76,91],"prevents":[77],"any":[78],"from":[80],"keeping":[81],"stressed":[82],"as":[84,96],"to":[85],"have":[86],"a":[87,101],"long":[88,97],"life.":[89],"has":[92],"more":[93],"than":[94,100],"twice":[95],"life":[98],"time":[99],"normal":[102],"FF.":[103],"Therefore,":[104],"SBFFs":[107],"improve":[108],"reliability":[110],"LSI":[113],"circuit.":[114]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
