{"id":"https://openalex.org/W2111333882","doi":"https://doi.org/10.1109/ismvl.2004.1319966","title":"Basic multiple-valued functions using recharge CMOS logic","display_name":"Basic multiple-valued functions using recharge CMOS logic","publication_year":2004,"publication_date":"2004-09-28","ids":{"openalex":"https://openalex.org/W2111333882","doi":"https://doi.org/10.1109/ismvl.2004.1319966","mag":"2111333882"},"language":"en","primary_location":{"id":"doi:10.1109/ismvl.2004.1319966","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2004.1319966","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103258590","display_name":"Yngvar Berg","orcid":"https://orcid.org/0000-0003-4519-995X"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":true,"raw_author_name":"Y. Berg","raw_affiliation_strings":["Department of Informatics, University of Oslo, Oslo, Norway"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026627174","display_name":"Snorre Aunet","orcid":"https://orcid.org/0000-0002-6465-8886"},"institutions":[{"id":"https://openalex.org/I204778367","display_name":"Norwegian University of Science and Technology","ror":"https://ror.org/05xg72x27","country_code":"NO","type":"education","lineage":["https://openalex.org/I204778367"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"S. Aunet","raw_affiliation_strings":["Norwegian, University of Science and Technology, Trondheim, Norway"],"affiliations":[{"raw_affiliation_string":"Norwegian, University of Science and Technology, Trondheim, Norway","institution_ids":["https://openalex.org/I204778367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065248078","display_name":"O. Noess","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"O. Noess","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5068390115","display_name":"Omid Mirmotahari","orcid":"https://orcid.org/0009-0003-2821-1088"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"O. Mirmotahari","raw_affiliation_strings":["Department of Informatics, University of Oslo, Oslo, Norway"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103258590"],"corresponding_institution_ids":["https://openalex.org/I184942183"],"apc_list":null,"apc_paid":null,"fwci":1.1446,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.78506621,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"346","last_page":"351"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6964829564094543},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.6940649747848511},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6857505440711975},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.6516545414924622},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5964682698249817},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5948339700698853},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5924773216247559},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.587912380695343},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5712441802024841},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5628474950790405},{"id":"https://openalex.org/keywords/emitter-coupled-logic","display_name":"Emitter-coupled logic","score":0.47557297348976135},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4731144607067108},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46390172839164734},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4567166566848755},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.43660375475883484},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.42548656463623047},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4221719205379486},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3959144353866577},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34266990423202515},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2250431776046753},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10583764314651489},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09800729155540466}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6964829564094543},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.6940649747848511},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6857505440711975},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.6516545414924622},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5964682698249817},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5948339700698853},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5924773216247559},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.587912380695343},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5712441802024841},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5628474950790405},{"id":"https://openalex.org/C11644886","wikidata":"https://www.wikidata.org/wiki/Q173552","display_name":"Emitter-coupled logic","level":5,"score":0.47557297348976135},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4731144607067108},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46390172839164734},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4567166566848755},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.43660375475883484},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.42548656463623047},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4221719205379486},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3959144353866577},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34266990423202515},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2250431776046753},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10583764314651489},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09800729155540466},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ismvl.2004.1319966","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2004.1319966","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1534694075","https://openalex.org/W1566416706","https://openalex.org/W1663816628","https://openalex.org/W1706200219","https://openalex.org/W2054208673","https://openalex.org/W2111719342","https://openalex.org/W2160142098"],"related_works":["https://openalex.org/W1968699962","https://openalex.org/W2099984297","https://openalex.org/W2084524856","https://openalex.org/W1538422785","https://openalex.org/W2350960814","https://openalex.org/W1593138522","https://openalex.org/W2102653533","https://openalex.org/W2112242076","https://openalex.org/W2121878746","https://openalex.org/W2102001671"],"abstract_inverted_index":{"In":[0,43],"this":[1,44],"paper,":[2,45],"we":[3],"present":[4],"novel":[5],"recharge":[6,18],"logic":[7,20,29,54,75],"for":[8,50,76],"multiple-valued":[9,19],"(MV)":[10],"systems":[11],"by":[12,67],"utilizing":[13],"semi-floating-gate":[14],"(SFG)":[15],"transistors.":[16],"The":[17,31,57],"can":[21],"be":[22],"used":[23],"to":[24,61,71],"implement":[25],"low-power":[26],"digital":[27,69],"transition":[28],"circuits.":[30],"improvement":[32],"in":[33,38],"power":[34,41,65],"dissipation":[35],"is":[36,60],"mainly":[37],"reduced":[39],"dynamic":[40],"dissipation.":[42],"the":[46,64],"basic":[47],"functions":[48],"suitable":[49,74],"synthesis":[51],"of":[52],"MV":[53],"are":[55],"presented.":[56],"main":[58],"purpose":[59],"level":[62],"out":[63],"dissipated":[66],"a":[68],"system":[70],"obtain":[72],"more":[73],"mixed":[77],"mode":[78],"design.":[79]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
