{"id":"https://openalex.org/W4229490312","doi":"https://doi.org/10.1109/ismvl.2004.1319931","title":"Signed digit CMOS (SD-CMOS) logic circuits with static operation","display_name":"Signed digit CMOS (SD-CMOS) logic circuits with static operation","publication_year":2004,"publication_date":"2004-09-28","ids":{"openalex":"https://openalex.org/W4229490312","doi":"https://doi.org/10.1109/ismvl.2004.1319931"},"language":"en","primary_location":{"id":"doi:10.1109/ismvl.2004.1319931","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2004.1319931","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077235594","display_name":"H. Fukuda","orcid":null},"institutions":[{"id":"https://openalex.org/I4210138839","display_name":"Nikki-Universal (Japan)","ror":"https://ror.org/03yvav120","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210138839"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"H. Fukuda","raw_affiliation_strings":["New Japan Radio Company Limited, Japan"],"affiliations":[{"raw_affiliation_string":"New Japan Radio Company Limited, Japan","institution_ids":["https://openalex.org/I4210138839"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5077235594"],"corresponding_institution_ids":["https://openalex.org/I4210138839"],"apc_list":null,"apc_paid":null,"fwci":0.3292,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.68121999,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"128","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8139238357543945},{"id":"https://openalex.org/keywords/diode-or-circuit","display_name":"Diode-or circuit","score":0.7862929105758667},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.7424740791320801},{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.6237099766731262},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.6222508549690247},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5848888158798218},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.582342803478241},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5721726417541504},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5176287293434143},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.505872905254364},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5026321411132812},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.49628740549087524},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.46783578395843506},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4400051236152649},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4397600293159485},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4159512221813202},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3753122091293335},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.364432692527771},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.33827757835388184},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.29007941484451294},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.22396346926689148},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.2149842083454132},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1477988362312317},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13385045528411865}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8139238357543945},{"id":"https://openalex.org/C171065743","wikidata":"https://www.wikidata.org/wiki/Q5279089","display_name":"Diode-or circuit","level":5,"score":0.7862929105758667},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.7424740791320801},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.6237099766731262},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.6222508549690247},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5848888158798218},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.582342803478241},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5721726417541504},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5176287293434143},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.505872905254364},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5026321411132812},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.49628740549087524},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.46783578395843506},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4400051236152649},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4397600293159485},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4159512221813202},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3753122091293335},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.364432692527771},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.33827757835388184},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.29007941484451294},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.22396346926689148},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2149842083454132},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1477988362312317},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13385045528411865}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ismvl.2004.1319931","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2004.1319931","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2054208673","https://openalex.org/W2128615926","https://openalex.org/W2145715240","https://openalex.org/W2158807610"],"related_works":["https://openalex.org/W2129746686","https://openalex.org/W2580743037","https://openalex.org/W4229490312","https://openalex.org/W1889611132","https://openalex.org/W1485027372","https://openalex.org/W2108907112","https://openalex.org/W2554253794","https://openalex.org/W2539423522","https://openalex.org/W2063575829","https://openalex.org/W2982660917"],"abstract_inverted_index":{"A":[0],"design":[1],"is":[2],"proposed":[3,41],"for":[4],"a":[5,21,46,52,58],"voltage-mode":[6],"signed":[7],"digit":[8],"CMOS":[9,33,54],"(SD-CMOS)":[10],"logic":[11,55],"circuit.":[12],"This":[13],"circuit":[14,42,63],"can":[15,27],"provide":[16],"stable,":[17],"static":[18],"operation":[19,66],"with":[20],"multi-voltage":[22],"power":[23,69],"supply,":[24],"and":[25,57,68],"it":[26],"be":[28],"fabricated":[29],"by":[30],"applying":[31],"standard":[32],"process":[34],"technology.":[35],"Key":[36],"components":[37],"based":[38],"on":[39],"the":[40,74],"design,":[43],"such":[44],"as":[45],"driver":[47],"circuit,":[48,51,56],"an":[49],"inverter":[50],"general":[53],"D-F/F":[59],"are":[60,71],"described.":[61],"Each":[62],"element":[64],"number,":[65],"speed,":[67],"consumption":[70],"examined":[72],"from":[73],"viewpoint":[75],"of":[76],"system":[77],"applications.":[78]},"counts_by_year":[{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
