{"id":"https://openalex.org/W2136041613","doi":"https://doi.org/10.1109/ismvl.2003.1201398","title":"Iterative symmetry indices decomposition for ternary logic synthesis in three-dimensional space","display_name":"Iterative symmetry indices decomposition for ternary logic synthesis in three-dimensional space","publication_year":2004,"publication_date":"2004-06-22","ids":{"openalex":"https://openalex.org/W2136041613","doi":"https://doi.org/10.1109/ismvl.2003.1201398","mag":"2136041613"},"language":"en","primary_location":{"id":"doi:10.1109/ismvl.2003.1201398","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2003.1201398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055373166","display_name":"Anas N. Al\u2010Rabadi","orcid":null},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A.N. Al-Rabadi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA","[Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA]","institution_ids":["https://openalex.org/I126345244"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5055373166"],"corresponding_institution_ids":["https://openalex.org/I126345244"],"apc_list":null,"apc_paid":null,"fwci":0.3292,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.65225726,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"139","last_page":"145"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6772533059120178},{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.6340659260749817},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5651963353157043},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5423283576965332},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5152199864387512},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.49939990043640137},{"id":"https://openalex.org/keywords/iterative-method","display_name":"Iterative method","score":0.4961174428462982},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.48747682571411133},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.4760008752346039},{"id":"https://openalex.org/keywords/symmetry","display_name":"Symmetry (geometry)","score":0.4550817906856537},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4285631477832794},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.39064541459083557},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.370698481798172},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10408145189285278},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.08372482657432556},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.07586324214935303},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.071746826171875}],"concepts":[{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6772533059120178},{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.6340659260749817},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5651963353157043},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5423283576965332},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5152199864387512},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.49939990043640137},{"id":"https://openalex.org/C159694833","wikidata":"https://www.wikidata.org/wiki/Q2321565","display_name":"Iterative method","level":2,"score":0.4961174428462982},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.48747682571411133},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.4760008752346039},{"id":"https://openalex.org/C2779886137","wikidata":"https://www.wikidata.org/wiki/Q21030012","display_name":"Symmetry (geometry)","level":2,"score":0.4550817906856537},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4285631477832794},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.39064541459083557},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.370698481798172},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10408145189285278},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.08372482657432556},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.07586324214935303},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.071746826171875},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ismvl.2003.1201398","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2003.1201398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W107987290","https://openalex.org/W130608904","https://openalex.org/W1543281322","https://openalex.org/W2012170251","https://openalex.org/W2117043478","https://openalex.org/W2148205480","https://openalex.org/W2167550974"],"related_works":["https://openalex.org/W2386022279","https://openalex.org/W2113700423","https://openalex.org/W3129977055","https://openalex.org/W2108229542","https://openalex.org/W3148292035","https://openalex.org/W2370649629","https://openalex.org/W1966764473","https://openalex.org/W2362510906","https://openalex.org/W1984491986","https://openalex.org/W1488117239"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"the":[3,6,13,33,49],"implementation":[4],"of":[5,15,22,35,51],"Iterative":[7],"Symmetry":[8],"Indices":[9],"Decomposition":[10],"(ISID)":[11],"for":[12,48],"synthesis":[14,21,34,50],"ternary":[16],"three-dimensional":[17,54],"logic":[18,56],"circuits.":[19],"The":[20,43],"regular":[23,55],"two-dimensional":[24],"circuits":[25,37,57],"using":[26,38,53],"ISID":[27,39],"has":[28,40],"been":[29,41],"introduced":[30],"previously,":[31],"and":[32],"area-specific":[36],"demonstrated":[42],"new":[44],"method":[45],"is":[46],"useful":[47],"functions":[52],"whenever":[58],"volume-specific":[59],"layout":[60],"constraints":[61],"have":[62],"to":[63],"be":[64],"satisfied.":[65]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
