{"id":"https://openalex.org/W2167554282","doi":"https://doi.org/10.1109/ismvl.2003.1201397","title":"A novel technology mapping method for AND/XOR expressions","display_name":"A novel technology mapping method for AND/XOR expressions","publication_year":2004,"publication_date":"2004-06-22","ids":{"openalex":"https://openalex.org/W2167554282","doi":"https://doi.org/10.1109/ismvl.2003.1201397","mag":"2167554282"},"language":"en","primary_location":{"id":"doi:10.1109/ismvl.2003.1201397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2003.1201397","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://digitalcommons.uri.edu/ele_facpubs/800","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054217230","display_name":"Seok\u2010Bum Ko","orcid":"https://orcid.org/0000-0002-9287-317X"},"institutions":[{"id":"https://openalex.org/I32625721","display_name":"University of Saskatchewan","ror":"https://ror.org/010x8gc63","country_code":"CA","type":"education","lineage":["https://openalex.org/I32625721"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Seok-Bum Ko","raw_affiliation_strings":["Department of EE, University of Saskatchewan, Saskatoon, SAS, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of EE, University of Saskatchewan, Saskatoon, SAS, Canada","institution_ids":["https://openalex.org/I32625721"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108527096","display_name":"Jien-Chung Lo","orcid":null},"institutions":[{"id":"https://openalex.org/I17626003","display_name":"University of Rhode Island","ror":"https://ror.org/013ckk937","country_code":"US","type":"education","lineage":["https://openalex.org/I17626003"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jien-Chung Lo","raw_affiliation_strings":["Department of ECE, University of Rhode Island, Kingston, RI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, University of Rhode Island, Kingston, RI, USA","institution_ids":["https://openalex.org/I17626003"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1912555,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"133","last_page":"138"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7971592545509338},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.77510666847229},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7692596912384033},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7564469575881958},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.7557172775268555},{"id":"https://openalex.org/keywords/exclusive-or","display_name":"Exclusive or","score":0.692775547504425},{"id":"https://openalex.org/keywords/bitwise-operation","display_name":"Bitwise operation","score":0.6261290907859802},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.5420795679092407},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5327677130699158},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.5222700238227844},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45256099104881287},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.44884029030799866},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43377089500427246},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.40529105067253113},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3584864139556885},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35848289728164673},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34642794728279114},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13778072595596313},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.11383354663848877},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08368957042694092}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7971592545509338},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.77510666847229},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7692596912384033},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7564469575881958},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.7557172775268555},{"id":"https://openalex.org/C35898486","wikidata":"https://www.wikidata.org/wiki/Q498186","display_name":"Exclusive or","level":3,"score":0.692775547504425},{"id":"https://openalex.org/C134765980","wikidata":"https://www.wikidata.org/wiki/Q879126","display_name":"Bitwise operation","level":2,"score":0.6261290907859802},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.5420795679092407},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5327677130699158},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.5222700238227844},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45256099104881287},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.44884029030799866},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43377089500427246},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.40529105067253113},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3584864139556885},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35848289728164673},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34642794728279114},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13778072595596313},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.11383354663848877},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08368957042694092},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ismvl.2003.1201397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2003.1201397","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:digitalcommons.uri.edu:ele_facpubs-1799","is_oa":true,"landing_page_url":"https://digitalcommons.uri.edu/ele_facpubs/800","pdf_url":null,"source":{"id":"https://openalex.org/S2764761010","display_name":"Journal of Media Literacy Education","issn_l":"2167-8715","issn":["2167-8715"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310316378","host_organization_name":"National Association for Media Literacy Education","host_organization_lineage":["https://openalex.org/P4310316378"],"host_organization_lineage_names":["National Association for Media Literacy Education"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical, Computer, and Biomedical Engineering Faculty Publications","raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:digitalcommons.uri.edu:ele_facpubs-1799","is_oa":true,"landing_page_url":"https://digitalcommons.uri.edu/ele_facpubs/800","pdf_url":null,"source":{"id":"https://openalex.org/S2764761010","display_name":"Journal of Media Literacy Education","issn_l":"2167-8715","issn":["2167-8715"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310316378","host_organization_name":"National Association for Media Literacy Education","host_organization_lineage":["https://openalex.org/P4310316378"],"host_organization_lineage_names":["National Association for Media Literacy Education"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical, Computer, and Biomedical Engineering Faculty Publications","raw_type":"text"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1506062186","https://openalex.org/W1604160780","https://openalex.org/W1677912025","https://openalex.org/W1911737408","https://openalex.org/W1974929108","https://openalex.org/W2038539185","https://openalex.org/W2052067881","https://openalex.org/W2089104196","https://openalex.org/W2130919049","https://openalex.org/W2133687702","https://openalex.org/W2143806343","https://openalex.org/W2313433831","https://openalex.org/W4252162212","https://openalex.org/W6630258170","https://openalex.org/W6637451613"],"related_works":["https://openalex.org/W264971478","https://openalex.org/W2362925226","https://openalex.org/W2350295618","https://openalex.org/W2167554282","https://openalex.org/W3185975600","https://openalex.org/W3193950766","https://openalex.org/W2083409928","https://openalex.org/W2404035422","https://openalex.org/W2383915326","https://openalex.org/W4313332205"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"a":[5,77],"novel":[6],"technology":[7,23,97],"mapping":[8,24,98],"technique":[9,25,102],"for":[10,72],"Look-Up":[11],"Table":[12],"(LUT)":[13],"-":[14],"based":[15,27],"Field":[16],"Programmable":[17],"Gate":[18],"Arrays":[19],"(FPGA).":[20],"The":[21,32,58,100],"proposed":[22,37,96,101,116],"is":[26,103,122,140],"on":[28],"AND/exclusive-OR":[29],"(XOR)":[30],"expressions.":[31],"AND/XOR":[33],"nature":[34],"of":[35,94,120,136],"the":[36,92,106,115,118,133,147],"techniques":[38],"can":[39],"map":[40],"many":[41],"important":[42],"XOR-intensive":[43,73],"applications,":[44],"such":[45],"as":[46],"error":[47],"detecting/correcting,":[48],"data":[49],"encryption/decryption,":[50],"and":[51,67,80,128,132],"computer":[52],"arithmetic":[53],"circuits":[54,86],"efficiently":[55],"in":[56,87],"FPGA.":[57],"typical":[59,107,148],"EDA":[60],"tools":[61],"deal":[62],"mainly":[63],"with":[64,109],"AND/OR":[65],"expressions":[66],"therefore":[68],"are":[69],"quite":[70],"inefficient":[71],"applications.":[74],"We":[75],"design":[76],"new":[78],"approach":[79],"conduct":[81],"experiments":[82],"using":[83,114],"MCNC":[84],"benchmark":[85],"FPGA":[88],"environment":[89],"to":[90,105,111,146],"demonstrate":[91],"effectiveness":[93],"our":[95],"technique.":[99],"superior":[104],"methods":[108],"respect":[110],"area.":[112],"When":[113],"technique,":[117],"number":[119,135],"CLB":[121],"reduced":[123,142],"by":[124,143],"67.6%":[125],"(speed-optimized":[126],"one)":[127,131],"57.7%":[129],"(area-optimized":[130],"total":[134],"equivalent":[137],"gate":[138],"counts":[139],"also":[141],"65.5%":[144],"compared":[145],"methods.":[149]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
