{"id":"https://openalex.org/W2144430402","doi":"https://doi.org/10.1109/ismvl.2002.1011100","title":"Multi-valued flip-flop with neuron-CMOS NMIN circuits","display_name":"Multi-valued flip-flop with neuron-CMOS NMIN circuits","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2144430402","doi":"https://doi.org/10.1109/ismvl.2002.1011100","mag":"2144430402"},"language":"en","primary_location":{"id":"doi:10.1109/ismvl.2002.1011100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2002.1011100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063846356","display_name":"M. Inaba","orcid":null},"institutions":[{"id":"https://openalex.org/I24254649","display_name":"Tsukuba University of Technology","ror":"https://ror.org/057bx9y85","country_code":"JP","type":"education","lineage":["https://openalex.org/I24254649"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Inaba","raw_affiliation_strings":["Department of Information Science and Electronics, Tsukuba College of Technology, Tsukuba, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Information Science and Electronics, Tsukuba College of Technology, Tsukuba, Japan","institution_ids":["https://openalex.org/I24254649"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101777998","display_name":"Koichi Tanno","orcid":"https://orcid.org/0000-0003-3548-5178"},"institutions":[{"id":"https://openalex.org/I118574687","display_name":"University of Miyazaki","ror":"https://ror.org/0447kww10","country_code":"JP","type":"education","lineage":["https://openalex.org/I118574687"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Tanno","raw_affiliation_strings":["Faculty of Engineering, Miyazaki University, Miyazaki, Japan"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Miyazaki University, Miyazaki, Japan","institution_ids":["https://openalex.org/I118574687"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072469129","display_name":"Okihiko Ishizuka","orcid":null},"institutions":[{"id":"https://openalex.org/I118574687","display_name":"University of Miyazaki","ror":"https://ror.org/0447kww10","country_code":"JP","type":"education","lineage":["https://openalex.org/I118574687"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"O. Ishizuka","raw_affiliation_strings":["Faculty of Engineering, Miyazaki University, Miyazaki, Japan"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Miyazaki University, Miyazaki, Japan","institution_ids":["https://openalex.org/I118574687"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5063846356"],"corresponding_institution_ids":["https://openalex.org/I24254649"],"apc_list":null,"apc_paid":null,"fwci":0.6954,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.73665234,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"7","issue":null,"first_page":"282","last_page":"288"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.7836984395980835},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6875986456871033},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6719786524772644},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6197605729103088},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5206496119499207},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4752640128135681},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.4652147591114044},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4194491505622864},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2609434127807617},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2507936358451843},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2128221094608307},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.17005029320716858},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10508909821510315}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.7836984395980835},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6875986456871033},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6719786524772644},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6197605729103088},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5206496119499207},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4752640128135681},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4652147591114044},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4194491505622864},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2609434127807617},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2507936358451843},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2128221094608307},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.17005029320716858},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10508909821510315}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ismvl.2002.1011100","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2002.1011100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1606203382","https://openalex.org/W2121631615","https://openalex.org/W2129069730","https://openalex.org/W2147911329","https://openalex.org/W2160142098"],"related_works":["https://openalex.org/W4382323155","https://openalex.org/W2262031297","https://openalex.org/W2733322820","https://openalex.org/W2482318635","https://openalex.org/W2020161494","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W2163601309","https://openalex.org/W2170979950","https://openalex.org/W1900707063"],"abstract_inverted_index":{"In":[0,62],"this":[1],"paper,":[2],"the":[3,8,12,26,31,38,56,67],"implementation":[4],"and":[5,30,52,79],"verification":[6,63],"of":[7,37],"fundamental":[9],"flip-flops":[10,69],"for":[11,59],"voltage-mode":[13],"multi-valued":[14,39,60],"logic":[15],"circuits":[16,29,51],"on":[17],"a":[18,45],"conventional":[19],"CMOS":[20],"VLSI":[21],"chip":[22],"are":[23,42,53],"presented.":[24],"Using":[25],"quantized":[27],"NMIN":[28,33],"analog":[32],"circuits,":[34],"two":[35],"types":[36],"R-S":[40,47],"flip-flop":[41,48,58],"designed":[43],"like":[44],"wide-use":[46],"with":[49,71],"NAND":[50],"applied":[54],"to":[55],"D":[57],"memory.":[61],"through":[64],"HSPICE":[65],"simulation,":[66],"proposed":[68],"perform":[70],"good":[72],"results":[73],"such":[74],"as":[75],"high":[76],"noise":[77],"margins":[78],"low":[80],"power":[81],"consumption.":[82]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}