{"id":"https://openalex.org/W2168273010","doi":"https://doi.org/10.1109/ismvl.2002.1011069","title":"Logic for static hazard detection of multiple-valued logic circuits with TSUM, MIN, and Literals","display_name":"Logic for static hazard detection of multiple-valued logic circuits with TSUM, MIN, and Literals","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2168273010","doi":"https://doi.org/10.1109/ismvl.2002.1011069","mag":"2168273010"},"language":"en","primary_location":{"id":"doi:10.1109/ismvl.2002.1011069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2002.1011069","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062255601","display_name":"N. Tkagi","orcid":null},"institutions":[{"id":"https://openalex.org/I63216439","display_name":"Toyama Prefectural University","ror":"https://ror.org/03xgh2v50","country_code":"JP","type":"education","lineage":["https://openalex.org/I63216439"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"N. Tkagi","raw_affiliation_strings":["Department of Electronics and Informatics, Toyama Prefectural University, Kosugi, Toyama, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Informatics, Toyama Prefectural University, Kosugi, Toyama, Japan","institution_ids":["https://openalex.org/I63216439"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015754641","display_name":"Kyoichi Nakashima","orcid":null},"institutions":[{"id":"https://openalex.org/I63216439","display_name":"Toyama Prefectural University","ror":"https://ror.org/03xgh2v50","country_code":"JP","type":"education","lineage":["https://openalex.org/I63216439"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Nakashima","raw_affiliation_strings":["Department of Electronics and Informatics, Toyama Prefectural University, Kosugi, Toyama, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Informatics, Toyama Prefectural University, Kosugi, Toyama, Japan","institution_ids":["https://openalex.org/I63216439"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5062255601"],"corresponding_institution_ids":["https://openalex.org/I63216439"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.15731212,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"46","last_page":"51"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10876","display_name":"Fault Detection and Control Systems","score":0.9793999791145325,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10876","display_name":"Fault Detection and Control Systems","score":0.9793999791145325,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9678000211715698,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11357","display_name":"Risk and Safety Analysis","score":0.9657999873161316,"subfield":{"id":"https://openalex.org/subfields/1804","display_name":"Statistics, Probability and Uncertainty"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6305862665176392},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6230167746543884},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.602179229259491},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5912718176841736},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5851527452468872},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5600427985191345},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5344613790512085},{"id":"https://openalex.org/keywords/hazard","display_name":"Hazard","score":0.5253048539161682},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49397093057632446},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.4691939055919647},{"id":"https://openalex.org/keywords/literal","display_name":"Literal (mathematical logic)","score":0.46886804699897766},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4241161346435547},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4135285019874573},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.41268569231033325},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3861730396747589},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28834068775177},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2635152041912079},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19677448272705078}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6305862665176392},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6230167746543884},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.602179229259491},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5912718176841736},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5851527452468872},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5600427985191345},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5344613790512085},{"id":"https://openalex.org/C49261128","wikidata":"https://www.wikidata.org/wiki/Q1132455","display_name":"Hazard","level":2,"score":0.5253048539161682},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49397093057632446},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.4691939055919647},{"id":"https://openalex.org/C2780882242","wikidata":"https://www.wikidata.org/wiki/Q14235582","display_name":"Literal (mathematical logic)","level":2,"score":0.46886804699897766},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4241161346435547},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4135285019874573},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.41268569231033325},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3861730396747589},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28834068775177},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2635152041912079},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19677448272705078},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ismvl.2002.1011069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.2002.1011069","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1483568252","https://openalex.org/W1983168617","https://openalex.org/W2025152094","https://openalex.org/W2054208673","https://openalex.org/W2132127141","https://openalex.org/W2143132439","https://openalex.org/W2145181205","https://openalex.org/W2165132873","https://openalex.org/W2181120999","https://openalex.org/W2496673401","https://openalex.org/W6646416624","https://openalex.org/W6724512002","https://openalex.org/W7048190923"],"related_works":["https://openalex.org/W2021357106","https://openalex.org/W2152533674","https://openalex.org/W2082591327","https://openalex.org/W2049889603","https://openalex.org/W2102653533","https://openalex.org/W1593138522","https://openalex.org/W2063209251","https://openalex.org/W2155174752","https://openalex.org/W2020551446","https://openalex.org/W1601832081"],"abstract_inverted_index":{"Multiple-valued":[0,114],"logic":[1,21,56,94,115],"circuits":[2,22,116],"are":[3,23,41,117],"often":[4],"implemented":[5],"by":[6,25,111,122],"the":[7,14,29,32,69,75,101,107,112,123,126,129],"current":[8,70],"mode":[9,16,71],"CMOS":[10,72],"technology,":[11,73],"or":[12],"sometimes":[13],"voltage":[15],"technology.":[17],"Even":[18],"if":[19],"multiple-valued":[20,55,93],"realized":[24],"either":[26],"one":[27],"of":[28,77,92,100,104],"two":[30],"technologies,":[31],"signal":[33],"propagation":[34],"delay":[35],"will":[36,49,97],"cause":[37],"hazards":[38,53,90],"pluses,":[39],"which":[40],"undesirable":[42],"short":[43],"pulses":[44],"in":[45,54],"circuits.":[46,57,95],"This":[47],"paper":[48,59],"focus":[50],"on":[51,106],"static":[52],"The":[58],"is":[60,81],"supposed":[61,118],"to":[62,84,119],"have":[63],"a":[64,86],"device":[65],"technology":[66],"such":[67],"as":[68],"because":[74],"way":[76],"information":[78],"signals":[79],"transition":[80],"very":[82],"important":[83],"introduce":[85],"logical":[87,108],"model":[88,109],"for":[89],"detection":[91],"We":[96],"show":[98],"some":[99],"mathematical":[102],"properties":[103],"functions":[105],"introduced":[110],"paper.":[113],"be":[120],"constructed":[121],"truncated":[124],"sum,":[125],"minimum,":[127],"and":[128],"literal":[130],"gates.":[131]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
