{"id":"https://openalex.org/W3192553137","doi":"https://doi.org/10.1109/islped52811.2021.9502484","title":"Statistical Optimization of Compute In-Memory Performance Under Device Variation","display_name":"Statistical Optimization of Compute In-Memory Performance Under Device Variation","publication_year":2021,"publication_date":"2021-07-26","ids":{"openalex":"https://openalex.org/W3192553137","doi":"https://doi.org/10.1109/islped52811.2021.9502484","mag":"3192553137"},"language":"en","primary_location":{"id":"doi:10.1109/islped52811.2021.9502484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped52811.2021.9502484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089938000","display_name":"Brian Crafton","orcid":"https://orcid.org/0000-0002-0227-0421"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Brian Crafton","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027137793","display_name":"Samuel Spetalnick","orcid":"https://orcid.org/0000-0003-1627-9002"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Samuel Spetalnick","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059199220","display_name":"Jong\u2010Hyeok Yoon","orcid":"https://orcid.org/0000-0001-7373-7028"},"institutions":[{"id":"https://openalex.org/I193352282","display_name":"Daegu Gyeongbuk Institute of Science and Technology","ror":"https://ror.org/03frjya69","country_code":"KR","type":"education","lineage":["https://openalex.org/I193352282"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jong-Hyeok Yoon","raw_affiliation_strings":["Daegu Gyeongbuk Institute of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Daegu Gyeongbuk Institute of Science and Technology","institution_ids":["https://openalex.org/I193352282"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091408102","display_name":"Arijit Raychowdhury","orcid":"https://orcid.org/0000-0001-8391-0576"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arijit Raychowdhury","raw_affiliation_strings":["Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5089938000"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.3008,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.56038227,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8997108936309814},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7424465417861938},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.5255826115608215},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5173791646957397},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.5003821849822998},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.49710944294929504},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4854491353034973},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.48020824790000916},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4694098234176636},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.45389461517333984},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4533991813659668},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44040626287460327},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.4240339398384094},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.41939157247543335},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30924877524375916},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3006651997566223},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2738661766052246},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10420361161231995},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09584283828735352},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0804782509803772}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8997108936309814},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7424465417861938},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.5255826115608215},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5173791646957397},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.5003821849822998},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.49710944294929504},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4854491353034973},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.48020824790000916},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4694098234176636},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.45389461517333984},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4533991813659668},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44040626287460327},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.4240339398384094},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41939157247543335},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30924877524375916},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3006651997566223},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2738661766052246},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10420361161231995},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09584283828735352},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0804782509803772},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/islped52811.2021.9502484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped52811.2021.9502484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.41999998688697815,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320333591","display_name":"Multidisciplinary University Research Initiative","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2518281301","https://openalex.org/W2787759178","https://openalex.org/W2914754358","https://openalex.org/W2945445229","https://openalex.org/W2946047477","https://openalex.org/W2966199719","https://openalex.org/W3049223108","https://openalex.org/W3111475881","https://openalex.org/W3132905918","https://openalex.org/W3135839634","https://openalex.org/W6781275091","https://openalex.org/W6787003673"],"related_works":["https://openalex.org/W2076211355","https://openalex.org/W2007070351","https://openalex.org/W2033811947","https://openalex.org/W2183989414","https://openalex.org/W1551399929","https://openalex.org/W2038212394","https://openalex.org/W2410132916","https://openalex.org/W2065076119","https://openalex.org/W2162174949","https://openalex.org/W2533127403"],"abstract_inverted_index":{"Compute":[0],"in-memory":[1],"(CIM)":[2],"is":[3],"a":[4,73],"promising":[5],"technique":[6],"that":[7],"minimizes":[8],"data":[9,66],"transport,":[10],"maximizes":[11],"memory":[12,21,33],"throughput,":[13],"and":[14,71,84,96],"performs":[15],"computation":[16],"on":[17,67,77],"the":[18,58],"bitline":[19],"of":[20,37,60],"sub-arrays.":[22],"Utilizing":[23],"embedded":[24],"non-volatile":[25],"memories":[26],"(eNVM)":[27],"such":[28],"as":[29],"resistive":[30],"random":[31],"access":[32],"(RRAM),":[34],"various":[35],"forms":[36],"neural":[38],"networks":[39],"can":[40],"be":[41],"implemented.":[42],"Unfortunately,":[43],"CIM":[44,87],"faces":[45],"new":[46,74],"challenges":[47],"traditional":[48],"CMOS":[49],"architectures":[50],"have":[51],"avoided.":[52],"In":[53],"this":[54],"work,":[55],"we":[56],"explore":[57],"impact":[59],"device":[61,78],"variation":[62,79],"(calibrated":[63],"with":[64],"measured":[65],"foundry":[68],"RRAM":[69],"arrays)":[70],"propose":[72],"algorithm":[75],"based":[76],"to":[80,92],"increase":[81],"both":[82],"performance":[83,98],"accuracy":[85],"for":[86],"designs.":[88],"We":[89],"demonstrate":[90],"up":[91],"36%":[93],"power":[94],"improvement":[95],"44%":[97],"improvement,":[99],"while":[100],"satisfying":[101],"any":[102],"error":[103],"constraint.":[104]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
