{"id":"https://openalex.org/W2971735931","doi":"https://doi.org/10.1109/islped.2019.8824954","title":"SHRIMP: Efficient Instruction Delivery with Domain Wall Memory","display_name":"SHRIMP: Efficient Instruction Delivery with Domain Wall Memory","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2971735931","doi":"https://doi.org/10.1109/islped.2019.8824954","mag":"2971735931"},"language":"en","primary_location":{"id":"doi:10.1109/islped.2019.8824954","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2019.8824954","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005044811","display_name":"Joonas Multanen","orcid":"https://orcid.org/0000-0003-4438-2031"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Joonas Multanen","raw_affiliation_strings":["Tampere University, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University, Finland","institution_ids":["https://openalex.org/I166825849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050272735","display_name":"Pekka J\u00e4\u00e4skel\u00e4inen","orcid":"https://orcid.org/0000-0001-5707-8544"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Pekka Jaaskelainen","raw_affiliation_strings":["Tampere University, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tampere University, Finland","institution_ids":["https://openalex.org/I166825849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090070224","display_name":"Asif Ali Khan","orcid":"https://orcid.org/0000-0002-5130-9855"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Asif Ali Khan","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070038996","display_name":"Fazal Hameed","orcid":"https://orcid.org/0000-0002-2763-8755"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Fazal Hameed","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030115692","display_name":"Jer\u00f3nimo Castrill\u00f3n","orcid":"https://orcid.org/0000-0002-5007-445X"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jeronimo Castrillon","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8222026824951172},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6199091076850891},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.560697615146637},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.5004584789276123},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4849136471748352},{"id":"https://openalex.org/keywords/shrimp","display_name":"Shrimp","score":0.48199763894081116},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34791111946105957},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3458365201950073},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.3123374581336975},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.26100999116897583},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23912790417671204}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8222026824951172},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6199091076850891},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.560697615146637},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.5004584789276123},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4849136471748352},{"id":"https://openalex.org/C2776841996","wikidata":"https://www.wikidata.org/wiki/Q1517781","display_name":"Shrimp","level":2,"score":0.48199763894081116},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34791111946105957},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3458365201950073},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.3123374581336975},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.26100999116897583},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23912790417671204},{"id":"https://openalex.org/C505870484","wikidata":"https://www.wikidata.org/wiki/Q180538","display_name":"Fishery","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/islped.2019.8824954","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2019.8824954","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},{"id":"pmh:oai:trepo.tuni.fi:10024/215598","is_oa":false,"landing_page_url":"https://trepo.tuni.fi/handle/10024/215598","pdf_url":null,"source":{"id":"https://openalex.org/S7407055260","display_name":"Trepo - Institutional Repository of Tampere University","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1935056755","https://openalex.org/W1981443800","https://openalex.org/W1983096721","https://openalex.org/W1994953389","https://openalex.org/W2005242923","https://openalex.org/W2017836239","https://openalex.org/W2057807751","https://openalex.org/W2079103493","https://openalex.org/W2136800915","https://openalex.org/W2808118451","https://openalex.org/W2913174568","https://openalex.org/W2955510233","https://openalex.org/W3100951578","https://openalex.org/W4292169167","https://openalex.org/W6680320015","https://openalex.org/W6760298172","https://openalex.org/W6764761187","https://openalex.org/W6987144925"],"related_works":["https://openalex.org/W2349791858","https://openalex.org/W2334181344","https://openalex.org/W2138847","https://openalex.org/W2401095501","https://openalex.org/W4249130715","https://openalex.org/W310629987","https://openalex.org/W2362277122","https://openalex.org/W254684032","https://openalex.org/W1848192231","https://openalex.org/W120214571"],"abstract_inverted_index":{"Domain":[0],"Wall":[1],"Memory":[2,56],"(DWM)":[3],"is":[4,68],"a":[5,71,93,101],"promising":[6],"emerging":[7],"memory":[8,19,76,95],"technology":[9],"but":[10],"suffers":[11],"from":[12],"the":[13,33,59,82,89],"expensive":[14],"shifts":[15,85],"needed":[16],"to":[17,32,39],"align":[18],"locations":[20],"with":[21,70,92],"access":[22],"ports.":[23],"Previous":[24],"work":[25],"on":[26,29],"DWM":[27,66],"concentrates":[28],"data,":[30],"while,":[31],"best":[34,90,102],"of":[35,84,104],"our":[36],"knowledge,":[37],"techniques":[38],"specifically":[40],"target":[41],"instruction":[42,61,73],"streams":[43],"have":[44],"not":[45],"yet":[46],"been":[47],"studied.":[48],"In":[49,97],"this":[50],"paper,":[51],"we":[52],"propose":[53],"Shift-Reducing":[54],"Instruction":[55],"Placement":[57],"(SHRIMP),":[58],"first":[60],"placement":[62],"strategy":[63],"suited":[64],"for":[65],"which":[67],"accompanied":[69],"supporting":[72],"fetch":[74],"and":[75],"architecture.":[77],"The":[78],"proposed":[79],"approach":[80],"reduces":[81],"number":[83],"by":[86],"40%":[87],"in":[88,107],"case":[91,103],"small":[94],"overhead.":[96],"addition,":[98],"SHRIMP":[99],"achieves":[100],"23%":[105],"reduction":[106],"total":[108],"cycle":[109],"counts.":[110]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}