{"id":"https://openalex.org/W2744606792","doi":"https://doi.org/10.1109/islped.2017.8009168","title":"A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders","display_name":"A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders","publication_year":2017,"publication_date":"2017-07-01","ids":{"openalex":"https://openalex.org/W2744606792","doi":"https://doi.org/10.1109/islped.2017.8009168","mag":"2744606792"},"language":"en","primary_location":{"id":"doi:10.1109/islped.2017.8009168","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2017.8009168","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101967869","display_name":"Subhendu Roy","orcid":"https://orcid.org/0000-0001-8554-563X"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Subhendu Roy","raw_affiliation_strings":["Cadence Design Systems, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, San Jose, CA, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071995111","display_name":"Yuzhe Ma","orcid":"https://orcid.org/0000-0002-3612-4182"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuzhe Ma","raw_affiliation_strings":["CSE Department, The Chinese University of Hong Kong, NT, Hong Kong"],"affiliations":[{"raw_affiliation_string":"CSE Department, The Chinese University of Hong Kong, NT, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100675222","display_name":"Jin Miao","orcid":"https://orcid.org/0000-0002-0150-4599"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jin Miao","raw_affiliation_strings":["Cadence Design Systems, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, San Jose, CA, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051340429","display_name":"Bei Yu","orcid":"https://orcid.org/0000-0001-6406-4810"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bei Yu","raw_affiliation_strings":["CSE Department, The Chinese University of Hong Kong, NT, Hong Kong"],"affiliations":[{"raw_affiliation_string":"CSE Department, The Chinese University of Hong Kong, NT, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101967869"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":1.0284,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.78027108,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9048869609832764},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7009939551353455},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.5081205368041992},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5042723417282104},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.48229148983955383},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4753964841365814},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.4232296347618103},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41590720415115356},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.41138726472854614},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40912696719169617},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3286638855934143},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.2238244116306305},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20067483186721802},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.16064849495887756},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13207802176475525},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07853084802627563}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9048869609832764},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7009939551353455},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.5081205368041992},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5042723417282104},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.48229148983955383},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4753964841365814},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.4232296347618103},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41590720415115356},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.41138726472854614},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40912696719169617},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3286638855934143},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2238244116306305},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20067483186721802},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.16064849495887756},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13207802176475525},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07853084802627563},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/islped.2017.8009168","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2017.8009168","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-120395","is_oa":false,"landing_page_url":"http://gateway.isiknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=LinksAMR&SrcApp=PARTNER_APP&DestLinkType=FullRecord&DestApp=WOS&KeyUT=000411105200016","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1963965124","https://openalex.org/W1979306010","https://openalex.org/W1981025032","https://openalex.org/W1994560221","https://openalex.org/W1997582549","https://openalex.org/W2054115349","https://openalex.org/W2061485512","https://openalex.org/W2083951140","https://openalex.org/W2101234009","https://openalex.org/W2106089733","https://openalex.org/W2121318693","https://openalex.org/W2131647018","https://openalex.org/W2140854523","https://openalex.org/W2141984024","https://openalex.org/W2147847555","https://openalex.org/W2163199256","https://openalex.org/W2168543008","https://openalex.org/W2168848751","https://openalex.org/W2293147384","https://openalex.org/W2330850558","https://openalex.org/W2345438070","https://openalex.org/W2540581201","https://openalex.org/W4235507382","https://openalex.org/W4255283007","https://openalex.org/W6675354045","https://openalex.org/W6683722355"],"related_works":["https://openalex.org/W2743305891","https://openalex.org/W2051886008","https://openalex.org/W2535520145","https://openalex.org/W1716153929","https://openalex.org/W4247760676","https://openalex.org/W3042858012","https://openalex.org/W3199828306","https://openalex.org/W3205162826","https://openalex.org/W3112090072","https://openalex.org/W1975701649"],"abstract_inverted_index":{"In":[0,57,146],"spite":[1],"of":[2,52,80,97,141,169,186],"maturity":[3],"to":[4,68,92,157,181],"the":[5,50,94,98,135,139,183,187,224],"modern":[6],"electronic":[7],"design":[8,24,27,86,132,175,221],"automation":[9],"(EDA)":[10],"tools,":[11],"optimized":[12],"designs":[13],"at":[14],"architectural":[15,76,113,165,202,227],"stage":[16],"may":[17],"become":[18],"sub-optimal":[19],"after":[20],"going":[21],"through":[22],"physical":[23,101,190,230],"flow.":[25],"Adder":[26],"has":[28],"been":[29],"such":[30],"a":[31,62,70,82,130,151,159,171,219],"long":[32],"studied":[33],"fundamental":[34],"problem":[35],"in":[36,75,100,164,189],"VLSI":[37],"industry":[38],"yet":[39],"designers":[40],"cannot":[41],"achieve":[42,122,211],"optimal":[43],"solutions":[44],"by":[45,106,195],"running":[46,108,197],"EDA":[47,109,198],"tools":[48,110,199],"on":[49],"set":[51,140],"available":[53,142],"prefix":[54,64,143,153],"adder":[55,65,144,154],"architectures.":[56,145],"this":[58,147],"paper,":[59,148],"we":[60,149],"enhance":[61,150],"state-of-the-art":[63,152],"synthesis":[66,155],"algorithm":[67,156],"obtain":[69,158],"much":[71,160],"wider":[72,161],"solution":[73,162],"space":[74,87,163,176],"domain.":[77,166],"On":[78,167],"top":[79,168],"that,":[81,170],"machine":[83,172],"learning":[84,173],"based":[85,174],"exploration":[88,177],"methodology":[89,178],"is":[90,104,179,193],"applied":[91,180],"predict":[93,182],"Pareto":[95,127,184,216],"frontier":[96,128,185,217],"adders":[99,188],"domain,":[102,191],"which":[103,192],"infeasible":[105,194],"exhaustively":[107,196],"for":[111,200],"innumerable":[112,201],"solutions.":[114,203],"Experimental":[115,204],"results":[116,205],"demonstrate":[117,206],"that":[118,207],"our":[119,208],"framework":[120,209],"can":[121,210],"near-optimal":[123,212],"delay":[124,213],"vs.":[125,214],"power/area":[126,215],"over":[129,218],"wide":[131,220],"space,":[133,222],"bridging":[134,223],"gap":[136,225],"between":[137,226],"architeon":[138],"andctural":[228],"and":[229],"designs.":[231]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
