{"id":"https://openalex.org/W4230416644","doi":"https://doi.org/10.1109/islped.2013.6629335","title":"Power reduction by aggressive synthesis design space exploration","display_name":"Power reduction by aggressive synthesis design space exploration","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W4230416644","doi":"https://doi.org/10.1109/islped.2013.6629335"},"language":"en","primary_location":{"id":"doi:10.1109/islped.2013.6629335","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629335","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012357226","display_name":"Matthew M. Ziegler","orcid":"https://orcid.org/0000-0002-9259-7304"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Matthew M. Ziegler","raw_affiliation_strings":["IBM T.J. Watson Research Center, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM T.J. Watson Research Center, NY, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041762641","display_name":"George Gristede","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"George D. Gristede","raw_affiliation_strings":["IBM T.J. Watson Research Center, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM T.J. Watson Research Center, NY, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072328031","display_name":"Victor Zyuban","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Victor V. Zyuban","raw_affiliation_strings":["IBM T.J. Watson Research Center, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM T.J. Watson Research Center, NY, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5012357226"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1823,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.82593491,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"421","last_page":"426"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ibm","display_name":"IBM","score":0.7557695508003235},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7233518362045288},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6845097541809082},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6507055163383484},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6338851451873779},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5747781991958618},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.5693296194076538},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5234289169311523},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5195175409317017},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5086784958839417},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4904627501964569},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4651679992675781},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4375160336494446},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43583235144615173},{"id":"https://openalex.org/keywords/iterative-design","display_name":"Iterative design","score":0.42595404386520386},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20824700593948364},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15656185150146484},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.13650354743003845},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11525323987007141}],"concepts":[{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.7557695508003235},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7233518362045288},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6845097541809082},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6507055163383484},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6338851451873779},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5747781991958618},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.5693296194076538},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5234289169311523},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5195175409317017},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5086784958839417},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4904627501964569},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4651679992675781},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4375160336494446},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43583235144615173},{"id":"https://openalex.org/C106246047","wikidata":"https://www.wikidata.org/wiki/Q4928435","display_name":"Iterative design","level":3,"score":0.42595404386520386},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20824700593948364},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15656185150146484},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.13650354743003845},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11525323987007141},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2778648169","wikidata":"https://www.wikidata.org/wiki/Q967768","display_name":"Compatibility (geochemistry)","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/islped.2013.6629335","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629335","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.5799999833106995,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2113254438","https://openalex.org/W2137589342","https://openalex.org/W2318529517","https://openalex.org/W4256152027"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W3146054601","https://openalex.org/W2037960874","https://openalex.org/W2269990635","https://openalex.org/W4285464654","https://openalex.org/W3013057549","https://openalex.org/W2906427691","https://openalex.org/W2507786429","https://openalex.org/W2072910550"],"abstract_inverted_index":{"An":[0],"increasing":[1],"focus":[2],"on":[3,36,68],"design":[4,9,13,17,33,47,53,59,72],"productivity":[5],"is":[6,18],"shifting":[7],"microprocessor":[8,82],"to":[10,64,78,83],"more":[11],"synthesis-centric":[12],"methodologies.":[14],"Low":[15],"power":[16,85,108],"also":[19],"rising":[20],"in":[21],"importance,":[22],"even":[23],"for":[24,46,55],"higher":[25],"performance":[26],"server":[27],"chips.":[28],"This":[29,93],"paper":[30,94],"proposes":[31],"a":[32],"methodology":[34,75,100],"capitalizing":[35],"the":[37,52,66,79,87,91,99],"relatively":[38],"low":[39],"cost":[40],"of":[41,71,90,98],"parallel":[42,56],"synthesis":[43],"job":[44],"submission":[45],"space":[48,60],"exploration.":[49],"By":[50],"tailoring":[51],"flow":[54],"and":[57],"iterative":[58],"exploration":[61],"we":[62],"attempt":[63],"maximize":[65],"return":[67],"investment":[69],"(ROI)":[70],"effort.":[73],"The":[74],"was":[76],"applied":[77],"IBM":[80],"POWER7+\u2122":[81],"save":[84],"during":[86],"second":[88],"release":[89],"chip.":[92],"provides":[95],"an":[96],"overview":[97],"as":[101,103],"well":[102],"chip":[104],"hardware":[105],"measurements":[106],"showing":[107],"savings.":[109]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
