{"id":"https://openalex.org/W4234251784","doi":"https://doi.org/10.1109/islped.2013.6629313","title":"Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs","display_name":"Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W4234251784","doi":"https://doi.org/10.1109/islped.2013.6629313"},"language":"en","primary_location":{"id":"doi:10.1109/islped.2013.6629313","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112593708","display_name":"Ping-Sheng Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Ping-Sheng Lin","raw_affiliation_strings":["Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114859256","display_name":"Yi-Jung Chen","orcid":"https://orcid.org/0000-0002-3646-7716"},"institutions":[{"id":"https://openalex.org/I193365169","display_name":"National Chi Nan University","ror":"https://ror.org/03ha6v181","country_code":"TW","type":"education","lineage":["https://openalex.org/I193365169"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Jung Chen","raw_affiliation_strings":["Department of Computer Science and Information Engineering, Nation Chi Nan University, Nantou, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, Nation Chi Nan University, Nantou, Taiwan","institution_ids":["https://openalex.org/I193365169"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046948316","display_name":"Chia-Lin Yang","orcid":"https://orcid.org/0000-0003-0091-5027"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Lin Yang","raw_affiliation_strings":["Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040956103","display_name":"Yi-Chang Lu","orcid":"https://orcid.org/0000-0002-7638-0367"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Chang Lu","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5112593708"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.3765131,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"304","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.837685227394104},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8097621202468872},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.7138203978538513},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5830533504486084},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5190920829772949},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45721861720085144},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.4330025017261505},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4142146706581116},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37230437994003296},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26310670375823975},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21875691413879395},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10764658451080322}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.837685227394104},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8097621202468872},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.7138203978538513},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5830533504486084},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5190920829772949},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45721861720085144},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.4330025017261505},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4142146706581116},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37230437994003296},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26310670375823975},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21875691413879395},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10764658451080322}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/islped.2013.6629313","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6899999976158142,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2071208935","https://openalex.org/W2126339718"],"related_works":["https://openalex.org/W3120961607","https://openalex.org/W4401568740","https://openalex.org/W2098207691","https://openalex.org/W3148568549","https://openalex.org/W1648516568","https://openalex.org/W361036515","https://openalex.org/W2135100917","https://openalex.org/W2018755015","https://openalex.org/W2024395993","https://openalex.org/W4214760333"],"abstract_inverted_index":{"The":[0],"three-dimensional":[1],"(3D)":[2],"integration":[3],"technology":[4,50],"that":[5],"utilizes":[6],"low-latency":[7],"and":[8,16,44,59],"high-density":[9],"Through-Silicon":[10],"Vias":[11],"(TSVs)":[12],"to":[13,29,39],"integrate":[14],"DRAMs":[15],"Chip-Multiprocessors(CMPs)":[17],"in":[18,35],"the":[19,31,40,47,53,64,72,79,89],"third":[20],"dimension":[21],"has":[22],"been":[23],"demonstrated":[24],"as":[25],"a":[26],"promising":[27],"way":[28],"mitigate":[30],"memory":[32],"wall":[33],"problem":[34],"CMPs.":[36],"In":[37],"addition":[38],"improved":[41],"interconnection":[42],"performance":[43],"heterogeneous":[45],"integration,":[46],"3D":[48,68,84],"IC":[49],"also":[51],"provides":[52],"advantages":[54],"of":[55,67,74,83,88],"high":[56],"packaging":[57],"density":[58,66],"small":[60],"chip":[61],"area.":[62],"However,":[63],"power":[65],"ICs":[69,85],"increases":[70],"with":[71],"number":[73],"active":[75],"devices.":[76],"Therefore,":[77],"alleviating":[78],"thermal":[80],"stress":[81],"issue":[82],"is":[86],"one":[87],"major":[90],"design":[91],"challenges.":[92]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}