{"id":"https://openalex.org/W4229905820","doi":"https://doi.org/10.1109/islped.2013.6629306","title":"Low-voltage low-overhead asynchronous logic","display_name":"Low-voltage low-overhead asynchronous logic","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W4229905820","doi":"https://doi.org/10.1109/islped.2013.6629306"},"language":"en","primary_location":{"id":"doi:10.1109/islped.2013.6629306","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004766125","display_name":"Akshay Sridharan","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Akshay Sridharan","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035758161","display_name":"Carl Sechen","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carl Sechen","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011769350","display_name":"Roozbeh Jafari","orcid":"https://orcid.org/0000-0002-6358-0458"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Roozbeh Jafari","raw_affiliation_strings":["Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5004766125"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.41312713,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.72796013,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"10","issue":null,"first_page":"261","last_page":"266"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7743031978607178},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7674145698547363},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7193202972412109},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.6109674572944641},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5258962512016296},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.506676971912384},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5052259564399719},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.49854326248168945},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.479608416557312},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46495354175567627},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4583738148212433},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.41185036301612854},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.4107435941696167},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3775292634963989},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3409852385520935},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31263720989227295},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.17808416485786438},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1580086648464203},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15399444103240967},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.14540556073188782},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.11060559749603271},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08529514074325562}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7743031978607178},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7674145698547363},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7193202972412109},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.6109674572944641},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5258962512016296},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.506676971912384},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5052259564399719},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.49854326248168945},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.479608416557312},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46495354175567627},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4583738148212433},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.41185036301612854},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.4107435941696167},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3775292634963989},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3409852385520935},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31263720989227295},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.17808416485786438},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1580086648464203},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15399444103240967},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.14540556073188782},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.11060559749603271},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08529514074325562},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/islped.2013.6629306","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.75}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1583778827","https://openalex.org/W1986553199","https://openalex.org/W2000067621","https://openalex.org/W2012272086","https://openalex.org/W2043318181","https://openalex.org/W2051973459","https://openalex.org/W2107103004","https://openalex.org/W2108400301","https://openalex.org/W2108924079","https://openalex.org/W2120733705","https://openalex.org/W2135446888","https://openalex.org/W2137541450","https://openalex.org/W2154277047","https://openalex.org/W2160160584","https://openalex.org/W2161331676","https://openalex.org/W2178247634","https://openalex.org/W2209490805","https://openalex.org/W2538518892","https://openalex.org/W4231905827","https://openalex.org/W4235838129","https://openalex.org/W4251660631","https://openalex.org/W6684805684"],"related_works":["https://openalex.org/W364924225","https://openalex.org/W60393894","https://openalex.org/W2095703739","https://openalex.org/W1993985975","https://openalex.org/W2093992207","https://openalex.org/W2325117947","https://openalex.org/W628161287","https://openalex.org/W158833317","https://openalex.org/W794031490","https://openalex.org/W2349909378"],"abstract_inverted_index":{"A":[0],"new":[1,94],"delay-bounded":[2],"asynchronous":[3,19,48,95,117],"logic":[4,20,36],"technique":[5],"aimed":[6],"at":[7,10,80],"maximizing":[8],"reliability":[9],"very":[11],"low":[12,81],"voltages":[13,82],"is":[14],"proposed.":[15],"Compared":[16,110],"to":[17,111],"previous":[18],"approaches,":[21],"the":[22,47,63,73,93,99,107,112,116],"area":[23,120],"and":[24,34,83],"nominal":[25],"delay":[26,43,64,131],"overheads":[27,121,132],"are":[28,39,54,66],"small.":[29],"Conventional":[30],"standard":[31],"cell":[32],"libraries":[33],"conventional":[35],"synthesis":[37],"tools":[38],"used.":[40],"The":[41],"bounding":[42],"elements":[44,65],"used":[45],"by":[46],"controller":[49],"feature":[50],"programmable":[51],"delays":[52],"that":[53],"initially":[55],"set":[56],"based":[57],"on":[58],"static":[59],"timing":[60],"analysis.":[61],"However,":[62],"updated":[67],"on-the-fly":[68],"during":[69],"actual":[70],"operation":[71],"of":[72],"circuit,":[74],"resulting":[75],"in":[76],"strong":[77],"resiliency":[78],"even":[79],"with":[84,92],"extreme":[85],"variations.":[86],"Several":[87],"benchmark":[88],"circuits":[89],"were":[90],"implemented":[91],"design":[96],"flow":[97],"using":[98],"45nm":[100],"TI":[101],"process.":[102],"Monte":[103],"Carlo":[104],"analysis":[105],"demonstrates":[106],"expected":[108],"resiliency.":[109],"equivalent":[113],"synchronous":[114],"circuits,":[115],"versions":[118],"have":[119],"averaging":[122],"40%,":[123],"although":[124],"much":[125],"smaller":[126],"for":[127],"large":[128],"circuits.":[129],"Nominal":[130],"average":[133],"about":[134],"10%.":[135]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}