{"id":"https://openalex.org/W4239157614","doi":"https://doi.org/10.1109/islped.2013.6629305","title":"Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology","display_name":"Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W4239157614","doi":"https://doi.org/10.1109/islped.2013.6629305"},"language":"en","primary_location":{"id":"doi:10.1109/islped.2013.6629305","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629305","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067819057","display_name":"Guerric de Streel","orcid":"https://orcid.org/0000-0001-7492-3113"},"institutions":[{"id":"https://openalex.org/I95674353","display_name":"UCLouvain","ror":"https://ror.org/02495e989","country_code":"BE","type":"education","lineage":["https://openalex.org/I95674353"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"Guerric de Streel","raw_affiliation_strings":["ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain-la-Neuve, Belgium"],"affiliations":[{"raw_affiliation_string":"ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain-la-Neuve, Belgium","institution_ids":["https://openalex.org/I95674353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065138463","display_name":"David Bol","orcid":"https://orcid.org/0000-0002-2678-1613"},"institutions":[{"id":"https://openalex.org/I95674353","display_name":"UCLouvain","ror":"https://ror.org/02495e989","country_code":"BE","type":"education","lineage":["https://openalex.org/I95674353"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"David Bol","raw_affiliation_strings":["ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain-la-Neuve, Belgium"],"affiliations":[{"raw_affiliation_string":"ICTEAM Institute, Universit\u00e9 catholique de Louvain, Louvain-la-Neuve, Belgium","institution_ids":["https://openalex.org/I95674353"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5067819057"],"corresponding_institution_ids":["https://openalex.org/I95674353"],"apc_list":null,"apc_paid":null,"fwci":2.6009,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.90894763,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"255","last_page":"260"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.9263019561767578},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.8422805070877075},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.8144787549972534},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.6687484383583069},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.6401915550231934},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5111623406410217},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47290050983428955},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4275832176208496},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.40463241934776306},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3019639551639557},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2871938943862915},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22711944580078125}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.9263019561767578},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8422805070877075},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.8144787549972534},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.6687484383583069},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.6401915550231934},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5111623406410217},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47290050983428955},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4275832176208496},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.40463241934776306},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3019639551639557},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2871938943862915},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22711944580078125},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/islped.2013.6629305","is_oa":false,"landing_page_url":"https://doi.org/10.1109/islped.2013.6629305","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Low Power Electronics and Design (ISLPED)","raw_type":"proceedings-article"},{"id":"pmh:oai:dial.uclouvain.be:boreal:152743","is_oa":false,"landing_page_url":"http://hdl.handle.net/2078.1/152743","pdf_url":null,"source":{"id":"https://openalex.org/S4306401902","display_name":"Digital Access to Libraries (Universit\u00e9 catholique de Louvain (UCL), l'Universit\u00e9 de Namur (UNamur) and the Universit\u00e9 Saint-Louis (USL-B))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I95674353","host_organization_name":"UCLouvain","host_organization_lineage":["https://openalex.org/I95674353"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1560300163","https://openalex.org/W1670085780","https://openalex.org/W1967171495","https://openalex.org/W1971662529","https://openalex.org/W2003986325","https://openalex.org/W2014067650","https://openalex.org/W2033255283","https://openalex.org/W2047418393","https://openalex.org/W2054702097","https://openalex.org/W2101383248","https://openalex.org/W2108312065","https://openalex.org/W2108519747","https://openalex.org/W2123262270","https://openalex.org/W2166252221","https://openalex.org/W4230854430","https://openalex.org/W4234830159","https://openalex.org/W6653991970","https://openalex.org/W6662316627","https://openalex.org/W6682521528"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2104885411","https://openalex.org/W2918058197"],"abstract_inverted_index":{"Minimum":[0,74],"energy":[1],"per":[2],"operation":[3,55],"is":[4],"typically":[5],"achieved":[6],"in":[7,49],"the":[8,24,68,98],"subthreshold":[9],"region":[10],"where":[11],"low":[12,15],"speed":[13],"and":[14,64,78],"robustness":[16],"are":[17],"two":[18],"challenging":[19],"problems.":[20],"This":[21],"paper":[22],"studies":[23],"impact":[25],"of":[26,51,54,70],"Back":[27],"Biasing":[28],"(BB)":[29],"schemes":[30],"on":[31,73],"these":[32],"features":[33],"for":[34],"FDSOI":[35],"technology.":[36],"We":[37],"show":[38],"that":[39],"Forward":[40],"BB":[41,61],"can":[42,66],"help":[43],"cover":[44],"a":[45,87,94],"wider":[46],"design":[47],"space":[48],"term":[50],"optimal":[52,81],"frequency":[53],"while":[56],"keeping":[57],"minimum":[58],"energy.":[59],"Asymmetric":[60],"between":[62],"NMOS":[63],"PMOS":[65],"mitigate":[67],"effect":[69],"systematic":[71],"mismatch":[72],"Energy":[75],"Point":[76],"(MEP)":[77],"robustness.":[79],"With":[80],"asymmetric":[82],"BB,":[83],"we":[84],"achieve":[85],"either":[86],"MEP":[88],"reduction":[89],"up":[90],"to":[91],"18%":[92],"or":[93],"36\u00d7":[95],"speedup":[96],"at":[97],"MEP.":[99]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
