{"id":"https://openalex.org/W2965041877","doi":"https://doi.org/10.1109/isie.2019.8781095","title":"HDL FSM Code Generation Using a MIPS-based Assembler","display_name":"HDL FSM Code Generation Using a MIPS-based Assembler","publication_year":2019,"publication_date":"2019-06-01","ids":{"openalex":"https://openalex.org/W2965041877","doi":"https://doi.org/10.1109/isie.2019.8781095","mag":"2965041877"},"language":"en","primary_location":{"id":"doi:10.1109/isie.2019.8781095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isie.2019.8781095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026610704","display_name":"Dominik Meyer","orcid":"https://orcid.org/0000-0002-6948-9858"},"institutions":[{"id":"https://openalex.org/I190134885","display_name":"Helmut Schmidt University","ror":"https://ror.org/04e8jbs38","country_code":"DE","type":"education","lineage":["https://openalex.org/I190134885"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dominik Meyer","raw_affiliation_strings":["Computer Engineering Faculty of Electrical Engineering, Helmut Schmidt University, Hamburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Faculty of Electrical Engineering, Helmut Schmidt University, Hamburg, Germany","institution_ids":["https://openalex.org/I190134885"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053568011","display_name":"Marcel Eckert","orcid":"https://orcid.org/0000-0002-2986-8327"},"institutions":[{"id":"https://openalex.org/I190134885","display_name":"Helmut Schmidt University","ror":"https://ror.org/04e8jbs38","country_code":"DE","type":"education","lineage":["https://openalex.org/I190134885"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Marcel Eckert","raw_affiliation_strings":["Computer Engineering Faculty of Electrical Engineering, Helmut Schmidt University, Hamburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Faculty of Electrical Engineering, Helmut Schmidt University, Hamburg, Germany","institution_ids":["https://openalex.org/I190134885"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087368086","display_name":"Bernd Klauer","orcid":null},"institutions":[{"id":"https://openalex.org/I190134885","display_name":"Helmut Schmidt University","ror":"https://ror.org/04e8jbs38","country_code":"DE","type":"education","lineage":["https://openalex.org/I190134885"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Bernd Klauer","raw_affiliation_strings":["Computer Engineering Faculty of Electrical Engineering, Helmut Schmidt University, Hamburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Faculty of Electrical Engineering, Helmut Schmidt University, Hamburg, Germany","institution_ids":["https://openalex.org/I190134885"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084589828","display_name":"Jan Haase","orcid":"https://orcid.org/0000-0003-3021-9217"},"institutions":[{"id":"https://openalex.org/I9341345","display_name":"University of L\u00fcbeck","ror":"https://ror.org/00t3r8h32","country_code":"DE","type":"education","lineage":["https://openalex.org/I9341345"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Haase","raw_affiliation_strings":["Institute of Computer Engineering, University of L\u00fcbeck, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of L\u00fcbeck, Germany","institution_ids":["https://openalex.org/I9341345"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1351","last_page":"1356"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8252625465393066},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8238251209259033},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6984995603561401},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6423689126968384},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6123302578926086},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5919724702835083},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5158666968345642},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49247488379478455},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.4679020345211029},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44927841424942017},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32322782278060913},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3229526877403259}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8252625465393066},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8238251209259033},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6984995603561401},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6423689126968384},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6123302578926086},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5919724702835083},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5158666968345642},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49247488379478455},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.4679020345211029},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44927841424942017},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32322782278060913},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3229526877403259},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isie.2019.8781095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isie.2019.8781095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2058650358","https://openalex.org/W2343695530","https://openalex.org/W2582517018","https://openalex.org/W2625826182"],"related_works":["https://openalex.org/W1493975478","https://openalex.org/W1650414576","https://openalex.org/W2110818533","https://openalex.org/W146887057","https://openalex.org/W1917852300","https://openalex.org/W2391435730","https://openalex.org/W2384838054","https://openalex.org/W2117342402","https://openalex.org/W2366672283","https://openalex.org/W2111408175"],"abstract_inverted_index":{"The":[0,32,52],"implementation":[1,34,53,101,116,128],"of":[2,14,74,80,89,103,117],"Finite":[3],"State":[4],"Machines":[5],"(FSMs)":[6],"is":[7,42,124],"a":[8,43,90],"recurring":[9],"task":[10],"in":[11,39,76],"the":[12,77,87,100,109,127,133],"development":[13],"embedded":[15],"systems":[16],"when":[17],"Field":[18],"Programmable":[19],"Gate":[20],"Arrays":[21],"(FPGAs)":[22],"or":[23,50,82],"Application":[24],"Specific":[25],"Integrated":[26],"Circuits":[27],"(ASICs)":[28],"are":[29,65],"being":[30],"designed.":[31],"standard":[33],"language":[35],"for":[36],"these":[37],"FSMs":[38,70,105,110],"this":[40],"context":[41],"Hardware":[44],"Description":[45],"Language":[46],"(HDL)":[47],"like":[48],"VHDL":[49,111,115],"Verilog.":[51],"complexity":[54,102],"can":[55],"rise":[56],"quickly":[57],"depending":[58],"on":[59],"FSM":[60],"size":[61],"and":[62,94],"which":[63],"devices/components":[64],"controlled.":[66],"In":[67],"many":[68],"cases":[69],"enforce":[71],"sequential":[72],"execution":[73],"instructions":[75],"concurrent":[78],"world":[79],"FPGAs":[81],"ASICs.":[83],"This":[84],"paper":[85],"proposes":[86],"use":[88],"MIPS-based":[91],"assembly":[92],"dialect":[93],"assembler":[95],"called":[96],"aFSM":[97,130],"to":[98,131],"decrease":[99],"such":[104],"by":[106],"automatically":[107],"generating":[108],"code.":[112],"A":[113],"human":[114],"an":[118,122],"Ethernet":[119],"controller":[120],"with":[121,129],"FPGA":[123],"compared":[125],"against":[126],"evaluate":[132],"assembler.":[134]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
