{"id":"https://openalex.org/W2580284127","doi":"https://doi.org/10.1109/isicir.2016.7829683","title":"A hardware framework for on-chip FPGA acceleration","display_name":"A hardware framework for on-chip FPGA acceleration","publication_year":2016,"publication_date":"2016-12-01","ids":{"openalex":"https://openalex.org/W2580284127","doi":"https://doi.org/10.1109/isicir.2016.7829683","mag":"2580284127"},"language":"en","primary_location":{"id":"doi:10.1109/isicir.2016.7829683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2016.7829683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043556227","display_name":"Andrea Lomuscio","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Lomuscio","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gian Carlo Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022318517","display_name":"Alberto Nannarelli","orcid":"https://orcid.org/0000-0002-8303-6329"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Alberto Nannarelli","raw_affiliation_strings":["DTU Compute, Technical University, Kongens Lyngby, Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DTU Compute, Technical University, Kongens Lyngby, Denmark","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Re","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1205,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.75839058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8768371343612671},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7421607971191406},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.7290927767753601},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.7099276781082153},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6458810567855835},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5496878027915955},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3824481964111328},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36957213282585144},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34919607639312744}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8768371343612671},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7421607971191406},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.7290927767753601},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.7099276781082153},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6458810567855835},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5496878027915955},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3824481964111328},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36957213282585144},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34919607639312744},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isicir.2016.7829683","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2016.7829683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/238597","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/238597","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7900000214576721,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1591070193","https://openalex.org/W1764493129","https://openalex.org/W2149611663","https://openalex.org/W2275125600","https://openalex.org/W2592821393","https://openalex.org/W6734248553"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2126857316","https://openalex.org/W2152074211","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1522032972","https://openalex.org/W2113308450","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2139962137"],"abstract_inverted_index":{"In":[0],"this":[1],"work,":[2],"we":[3,23,33],"present":[4],"a":[5,18],"new":[6],"framework":[7,56],"to":[8,40,65,72,82],"dynamically":[9],"load":[10,24],"hardware":[11],"accelerators":[12],"on":[13,57],"reconfigurable":[14,60],"platforms":[15],"(FPGAs).":[16],"Provided":[17],"library":[19],"of":[20],"application-specific":[21,79],"processors,":[22,80],"on-the-fly":[25],"the":[26,30,35,38,41,53,66,74,78,83],"specific":[27],"processor":[28],"in":[29,77],"FPGA,":[31],"and":[32,81],"transfer":[34],"execution":[36],"from":[37],"CPU":[39],"FPGA-based":[42],"accelerator.":[43],"Results":[44],"show":[45],"that":[46],"significant":[47],"speed-up":[48,69],"can":[49],"be":[50],"obtained":[51],"by":[52],"proposed":[54],"acceleration":[55,76],"system-on-chips":[58],"where":[59],"fabric":[61],"is":[62,70],"placed":[63],"next":[64],"CPUs.":[67],"The":[68],"due":[71],"both":[73],"intrinsic":[75],"increased":[84],"parallelism.":[85]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2017-02-03T00:00:00"}