{"id":"https://openalex.org/W2551478346","doi":"https://doi.org/10.1109/isicir.2014.7029575","title":"Twenty years of research on RNS for DSP: Lessons learned and future perspectives","display_name":"Twenty years of research on RNS for DSP: Lessons learned and future perspectives","publication_year":2014,"publication_date":"2014-12-01","ids":{"openalex":"https://openalex.org/W2551478346","doi":"https://doi.org/10.1109/isicir.2014.7029575","mag":"2551478346"},"language":"en","primary_location":{"id":"doi:10.1109/isicir.2014.7029575","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2014.7029575","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059417991","display_name":"P. Albicocco","orcid":"https://orcid.org/0000-0001-6430-1038"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Pietro Albicocco","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gian Carlo Cardarilli","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022318517","display_name":"Alberto Nannarelli","orcid":"https://orcid.org/0000-0002-8303-6329"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Alberto Nannarelli","raw_affiliation_strings":["Danmarks Tekniske Universitet, Lyngby, DK"],"affiliations":[{"raw_affiliation_string":"Danmarks Tekniske Universitet, Lyngby, DK","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Re","raw_affiliation_strings":["Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \u201cTor Vergata\u201d, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Department of Electronic Engineering, University of Rome \"Tor Vergata\", Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5059417991"],"corresponding_institution_ids":["https://openalex.org/I116067653"],"apc_list":null,"apc_paid":null,"fwci":6.3112,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.96427212,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"34","issue":null,"first_page":"436","last_page":"439"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9889000058174133,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6678913831710815},{"id":"https://openalex.org/keywords/microelectronics","display_name":"Microelectronics","score":0.6473596096038818},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6160097718238831},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5912457704544067},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5871483087539673},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5267031788825989},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5211774706840515},{"id":"https://openalex.org/keywords/residue-number-system","display_name":"Residue number system","score":0.47014644742012024},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44945210218429565},{"id":"https://openalex.org/keywords/obsolescence","display_name":"Obsolescence","score":0.42178159952163696},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3287695348262787},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26645416021347046},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2510574758052826},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19325989484786987}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6678913831710815},{"id":"https://openalex.org/C187937830","wikidata":"https://www.wikidata.org/wiki/Q175403","display_name":"Microelectronics","level":2,"score":0.6473596096038818},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6160097718238831},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5912457704544067},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5871483087539673},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5267031788825989},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5211774706840515},{"id":"https://openalex.org/C71480937","wikidata":"https://www.wikidata.org/wiki/Q3086516","display_name":"Residue number system","level":2,"score":0.47014644742012024},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44945210218429565},{"id":"https://openalex.org/C30795975","wikidata":"https://www.wikidata.org/wiki/Q282744","display_name":"Obsolescence","level":2,"score":0.42178159952163696},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3287695348262787},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26645416021347046},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2510574758052826},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19325989484786987},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/isicir.2014.7029575","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isicir.2014.7029575","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Symposium on Integrated Circuits (ISIC)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.704.9728","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.704.9728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www2.compute.dtu.dk/%7Ealna/pubs/isic14.pdf","raw_type":"text"},{"id":"pmh:oai:art.torvergata.it:2108/242181","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/242181","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/7c1e36b9-9776-46ed-9c07-62451c66192f","is_oa":false,"landing_page_url":"https://orbit.dtu.dk/en/publications/7c1e36b9-9776-46ed-9c07-62451c66192f","pdf_url":null,"source":{"id":"https://openalex.org/S4306400705","display_name":"Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I96673099","host_organization_name":"Technical University of Denmark","host_organization_lineage":["https://openalex.org/I96673099"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Albicocco , P , Cardarilli , G C , Nannarelli , A & Re , M 2014 , Twenty Years of Research on RNS for DSP: Lessons Learned and Future Perspectives . in Proceedings of the 14th International Symposium on Integrated Circuits (ISIC 2014) . IEEE , pp. 436-439 , 14th International Symposium on Integrated Circuits , Singapore , Singapore , 10/12/2014 . https://doi.org/10.1109/ISICIR.2014.7029575","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W581478192","https://openalex.org/W1489433220","https://openalex.org/W1591106557","https://openalex.org/W1996708669","https://openalex.org/W2096465027","https://openalex.org/W2109501945","https://openalex.org/W2130409149","https://openalex.org/W2147048722","https://openalex.org/W2148682337","https://openalex.org/W2149043711","https://openalex.org/W2161864301","https://openalex.org/W2539463133","https://openalex.org/W2542706582","https://openalex.org/W4243810185","https://openalex.org/W4253011160"],"related_works":["https://openalex.org/W4285293690","https://openalex.org/W3124382960","https://openalex.org/W1590264876","https://openalex.org/W1570681957","https://openalex.org/W3131858951","https://openalex.org/W2148208586","https://openalex.org/W2122536701","https://openalex.org/W2104644060","https://openalex.org/W1955329053","https://openalex.org/W1982296625"],"abstract_inverted_index":{"In":[0,25,82],"this":[1,83],"paper,":[2,84],"we":[3,85,128],"discuss":[4],"a":[5,71,87],"number":[6,88],"of":[7,74,89,94,115,119],"issues":[8],"emerged":[9],"from":[10,113,121],"our":[11],"twenty-year":[12],"long":[13],"experience":[14],"in":[15,37,55,64,135,143],"applying":[16],"the":[17,34,75,92,97],"Residue":[18],"Number":[19],"System":[20],"(RNS)":[21],"to":[22,32,44,106,109,117,124],"DSP":[23],"systems.":[24,146],"early":[26],"days,":[27],"RNS":[28,40,95,131],"was":[29],"mainly":[30],"used":[31,43],"reach":[33],"maximum":[35],"performance":[36],"speed.":[38],"Today,":[39],"is":[41],"also":[42],"obtain":[45],"power-efficient":[46],"(tradeoffs":[47],"speed-power)":[48],"and":[49,57,70,104,141],"reliable":[50,137],"systems":[51],"(redundant":[52],"RNS).":[53],"Advances":[54],"microelectronics":[56],"CAD":[58],"tools":[59],"play":[60],"an":[61],"important":[62],"role":[63],"favoring":[65],"one":[66],"technology":[67,101],"over":[68],"another,":[69],"winning":[72,98],"choice":[73,93],"past":[76],"may":[77],"become":[78],"at":[79],"disadvantage":[80],"today.":[81],"address":[86],"factors":[90],"influencing":[91],"as":[96],"solution.":[99],"From":[100],"platforms":[102],"(ASIC":[103],"FPGA),":[105],"issue":[107],"related":[108],"modern":[110],"design":[111],"tools,":[112],"cost":[114,118],"memory,":[116],"wiring,":[120],"power":[122],"dissipation":[123],"thermal":[125],"issues.":[126],"Moreover,":[127],"mention":[129],"how":[130],"can":[132],"be":[133],"helpful":[134],"implementing":[136],"architectures":[138],"(fault":[139],"detection":[140],"correction)":[142],"future":[144],"VLSI":[145]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}